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Voltage Controlled Variable Strained Silicon Die

IP.com Disclosure Number: IPCOM000124178D
Publication Date: 2005-Apr-11
Document File: 2 page(s) / 56K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a new strain forming mechanism for the strained silicon process. This process applies different voltages to the piezoelectric layer in order to change the strain level in the silicon. Benefits include a solution that has adaptive control over the active strain.

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Voltage Controlled Variable Strained Silicon Die

Disclosed is a method for a new strain forming mechanism for the strained silicon process. This process applies different voltages to the piezoelectric layer in order to change the strain level in the silicon. Benefits include a solution that has adaptive control over the active strain.

Background

Currently, there is a need to improve the ability to control the strain level in silicon. The current state of the art controls the stress via the deposited thin-film.

General Description

The disclosed method applies different voltages to the piezoelectric layer in order to change the strain level in the silicon. The voltage can be either DC or AC, depending on the application, and in a variety of electrical forms (e.g. pulsed tone burst, etc.) Sophisticated feedback controls contain both piezoelectric voltages and performance measures of a dummy or transistor on the silicon die. By forming in-plane compressive or tensile stresses, the mobility of gate channels is controlled in real-time. Figures 1 through 3 show different implementations of the disclosed method:

§         In Figure 1, the piezoelectric layer is placed at the back side of the silicon die. The piezoelectric is polarized by thickness, and the electrodes are placed on the top and bottom surfaces of the piezoelectric. When the voltage is applied across the piezoelectric, the formed in-plane stress (Trr) causes the silicon die mask to bend and form in-plane strains (Srr and SФФ...