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Method for patterned silicon via structures with insulating sidewalls for through-silicon via applications

IP.com Disclosure Number: IPCOM000124180D
Publication Date: 2005-Apr-11
Document File: 4 page(s) / 474K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for patterned silicon via structures with insulating sidewalls for through-silicon via applications. Benefits include improved functionality and improved performance.

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Method for patterned silicon via structures with insulating sidewalls for through-silicon via applications

Disclosed is a method for patterned silicon via structures with insulating sidewalls for through-silicon via applications. Benefits include improved functionality and improved performance.

Background

              The conventional solution for silicon vias with insulating sidewalls includes a deposited nitride spacer and an oxide hard mask (HM). The via etch profile is very straight with no HM undercut. Several etch steps are performed to break through the via bottom to make the electrical connection between two bonded wafers. During the etch process, the edge corner of the via can erode and expose the silicon substrate (red dotted area, see Figure 1). Because the corner is the electrical path to the adjacent via, high current leakage results.

      To mitigate the current leakage, thicker nitride spacer deposition has been used to passivate the silicon via sidewall. However, if the deposition is too thick, the nitride spacer may crack. Additionally, the top via critical dimension becomes too small due to the overhang that is formed.

General description

              The disclosed method patterns silicon via structures with insulating sidewalls for through-silicon via applications, such as 3-D interconnection (wafer bonding).

              The key elements of the disclosed method include:

•             Integration of wafer-to-wafer bonding to reduce the signal path distance and reduce the signal delay between two separate devices

•             Electrical connection between two wafers by silicon via (through-silicon via)

•             Sidewall insulation before Cu barrier layer deposition in the silicon via

•             Hard-mask undercut created during the deep silicon via etch process

•             Continuous fill of the via sidewall and hard-mask undercut using a nitride layer

•             Reten...