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Fabrication of Gate-First MOSFETs with New Gate-Stack Materials that Cannot Withstand High-Temperature Annealing

IP.com Disclosure Number: IPCOM000124188D
Publication Date: 2005-Apr-11
Document File: 3 page(s) / 213K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method that combines known semiconductor processing techniques to enable metal gate and/or high-potassium dielectric gate-first MOSFET fabrication. Benefits include enabling conventional process flows.

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Fabrication of Gate-First MOSFETs with New Gate-Stack Materials that Cannot Withstand High-Temperature Annealing

Disclosed is a method that combines known semiconductor processing techniques to enable metal gate and/or high-potassium dielectric gate-first MOSFET fabrication. Benefits include enabling conventional process flows.

Background

Most metal gate materials and high-potassium dielectrics have limited thermal stability on silicon, and cannot withstand high the temperatures needed for SD dopant activation (e.g. typically > 900oC). Currently, there is no clear solution for incorporating such advanced gate materials into a conventional CMOS process flow.

General Description

The disclosed method combines known semiconductor processing techniques to enable metal gate and/or high-potassium dielectric gate-first MOSFET fabrication. Figures 1 through 5 show the process steps for making the disclosed method.

The high-temperature plasma implantation of SD dopants enables the re-growth of damaged material as the dopants are implanted. This also enables dopants to be activated at the implantation temperature. Temperatures as low as 525oC can be used to fully re-crystallize the implanted silicon and achieve high levels of dopant activation.

Since conventional process flows use very high temperature activation (i.e. 1000oC), metal gates cannot be used in such a flow. The disclosed method can enable a gate-first, metal-gate process if maximum post metal temperature is limited to 500o...