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A Transistor with Improved Poly-Depletion and Short Channel Behavior

IP.com Disclosure Number: IPCOM000124195D
Publication Date: 2005-Apr-11
Document File: 3 page(s) / 171K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method that enables the decoupling of the doping implantation process conditions of the poly Gate from the doping of the source and drain of a CMOS device. Benefits include increasing the energy during the poly doping step, and decreasing the energy in the source and drain doping step.

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A Transistor with Improved Poly-Depletion and Short Channel Behavior

Disclosed is a method that enables the decoupling of the doping implantation process conditions of the poly Gate from the doping of the source and drain of a CMOS device. Benefits include increasing the energy during the poly doping step, and decreasing the energy in the source and drain doping step.

Background

The state of the art transistor fabrication process includes a litho and implant process steps for doping simultaneously the poly gate and source/drain (S/D). Following these two steps, an activation/diffusion thermal anneal is used to activate and diffuse the doping in both the poly gate oxide interface and the S/D region. Ideally, the diffusion in the poly needs to be maximized to achieve better poly depletion, while diffusion needs to be minimized in the S/D to allow for a better device short channel efffect (SCE) and scalability.

Currently, tradeoffs between poly thickness and dopant implant energy are carefully established to achieve the lowest possible poly depletion while containing the doping overrun from the S/D region into the channel. Often times in order to meet scalability requirements poly depletion is not fully minimized, which results in a thicker-than-desired device electrical gate oxide thickness and loss in device performance.

General Description

The disclosed method decouples the doping implantation process conditions of the poly gate from the doping of the S/D of a CMOS device. The disclosed method is for NMOS transistors, but can easily be extended to PMOS transistor devices. The...