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Cycle-Efficient Implementation of Diagonal Interleaver for GSM/GPRS Radio

IP.com Disclosure Number: IPCOM000124291D
Publication Date: 2005-Apr-14
Document File: 3 page(s) / 24K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method that uses a forward error correction (FEC) technique to encode multiple code words, and to shuffle or interleave the encoded bits. Benefits include doubling the data rates for real-time applications without increasing the memory requirements.

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Cycle-Efficient Implementation of Diagonal Interleaver for GSM/GPRS Radio

Disclosed is a method that uses a forward error correction (FEC) technique to encode multiple code words, and to shuffle or interleave the encoded bits. Benefits include doubling the data rates for real-time applications without increasing the memory requirements.

Background

Interleaving is a method of reordering the symbols in a group of transmitted code words, such that adjacent symbols in the data stream are not from the same code word. The receiver re-assembles or de-interleaves the code words. The bit interleaving process helps to reduce the effect of burst errors. It may be implemented as a convolutional interleaver or a block interleaver, depending upon whether the data is processed in a continuous stream or in a discrete stream. The simpler Block interleavers (BI) are widely used in wireless applications (e.g. GSM/ EGPRS/ WCDMA; Reed-Solomon/ Turbo Code).

The BI configures the memory as a matrix of n symbols (rows) by m code words (columns); during the write cycle, the input symbols are written column-wise; during a read cycle, the output symbols are read row-wise. The column length is usually equal to the code word length of the FEC encoder, while the numbers of rows (span) is the interleaver delay. Block interleaving may be rectangular (i.e. no data block interleaved with any other) or diagonal (i.e. one data block interleaved with one or more). Diagonal interleaving (DI) helps faster synchronization. The key performance parameters of the BI are its minimum (dispersing) distance, its computational and memory requirements, and its block delay (latency).

General Description

The disclosed method uses a memory-efficient implementation of BI for reducing its DSP cycles by about 50% over the existing solution. The disclosed method can be readily extended to other BIs and block de-interleavers; further, a hardware implementation is also feasible. The reduction in DSP cycles is achieved by reformulating the memory access pattern needed for the bit shuffling to:

 

  • reorder the nested loops and  simplify the accesses
  • minimize the table lookup and modulo-operations on variables
  • dissolve the inner-most loop to reduce their instructions.

With the disclosed method, the DI needs about 2 cycles per interleaved bit. 

The disclosed method uses the 22D4 Diagonal Interleaver. By integrating the interleaver into the loops of coding algorithm, the wasted cycles due to interleaver call overhead can be eliminated. The common approach for implementing a general BI is to use an interleaver look-up table. Each entry of the table is the offset to the location in the data buffer from which the current value should be read. The data is read by using the base address of the data buffer and the offset retrieved from the interleaver table. However, this operation is quite expensive in cycle’s consumption. The disclosed method uses a faster, incremental form...