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Method for the digital domain of a fractional-N PLL synthesizer

IP.com Disclosure Number: IPCOM000124315D
Publication Date: 2005-Apr-15
Document File: 4 page(s) / 45K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for the digital domain of a fractional-N (FN) phase-locked loop (PLL) synthesizer. Benefits include improved functionality, improved performance, and improved power performance.

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Method for the digital domain of a fractional-N PLL synthesizer

Disclosed is a method for the digital domain of a fractional-N (FN) phase-locked loop (PLL) synthesizer. Benefits include improved functionality, improved performance, and improved power performance.

Background

              A conventional 8-PSK FN synthesizer performs the following functions (see Figure 1):

1.           Packs the input bits into digital symbols.

2.           Incremental quantization (I/Q) components of the symbol phaser are produced by using a dedicated look-up table (LUT).
3.           I/Q components are passed through finite impulse response (FIR) shape filters to produce the base-band signal.
4.           Base-band signal is converted from the Cartesian domain to the Polar domain, where it is represented by the amplitude and phase components.
5.           Amplitude component goes through a delta-sigma (DS) converter and an analog low-pass filter (LPF) to feed the power amplifier (PA).
6.           Phase component is differentiated and converted into the frequency component.
7.           Frequency component is predistorted by a predistortion filter (PDF) to compensate for the changing impairments of the analog components of the system. (The PDF must be programmable).
8.           Frequency offset, which is the carrier frequency, is added to the signal, and the sum is fed to a DS converter to control the phase output of a fractional-N PLL (FN PLL).
9.           Output from the voltage controlled oscillator (VCO) of the PLL feeds the frequency input of the PA.

              The implementation of the digital domain becomes quite complicated, and requires a big silicon area for the following reasons:

•             To meet the tight requirements for phase noise and quantization, noise must be kept to a minimum, which requires 10-22 bits of accuracy for the different signals in the digital domain.

•             The shape filter must be at least four symbols in length. If 8 samples per symbols are used for the sampling rate, more than 30 taps are required in every filter.

•             The Cartesian-to-Polar converter requires more than 25 KG of silicon (~0.33 mm2).

              The final sampling rate at the delta-sigma output should be the same as the PLL reference frequency (typically 26 MHz). Interpolators are usually required in different parts of the digital domain because the symbol frequency is only ~271 KHz. Additionally, this conventional architecture leads to multiple clock domain designs, which complicate the implementation.

 


General description

              The disclosed method is the digital domain of an FN RF Synthesizer. The method uses more digital circuits and fewer analog circuits than the conventional solution by performing the signal synthesis directly in delta-sigma format by using appropriate LUTs. As a result, the silicon area is reduced significantly.

Advantages

              The disclosed method provides advantages, including:
•             Improved functionality due to reducing the required silicon sur...