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A method to Avoid Bus Contention in an Embedded Host Adapter Using a Software Algorithm for Throttling

IP.com Disclosure Number: IPCOM000124381D
Original Publication Date: 2005-Apr-18
Included in the Prior Art Database: 2005-Apr-18
Document File: 1 page(s) / 20K

Publishing Venue

IBM

Abstract

A method to avoid bus contention in an embedded host adapter using a software algorithm for throttling

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A method to Avoid Bus Contention in an Embedded Host Adapter Using a Software Algorithm for Throttling

Disclosed is a method of avoiding bus contention in an embedded host adapter by using a software algorithm to throttle bus contention.

In an embedded host adapter, the processor moves data from an externally connected host out a bus interface that is connected to a control unit. Under certain circumstances involving high stress, this bus interface can become overloaded and the host adapter may not be able to put data out on the bus as fast as it can generate it. In these cases, internal FIFO queues in the adapter back up. When these queues back up, the processor can experience 'starvation' from accessing anything (even its own memory) until the bus becomes free.

The idea behind this method is to utilize hardware functionality built into the embedded host adapter's bridge controller. At a selectable level, when the outbound buffer (FIFO) becomes full to a certain level, the processor will be interrupted, and the software algorithm to throttle data will be invoked. This algorithm will, on the interrupt context, poll the outgoing buffer to see when it is safe again for the application level code to send more data.

In this scenario, the embedded host adapter is running application level code, generating a large amount of data on its bus interface. Due to an external condition, the rate at which data is leaving the adapter begins to slow. The FIFO begins to fill to t...