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Browse Prior Art Database

MCSL and MSSA Test Mode

IP.com Disclosure Number: IPCOM000124387D
Original Publication Date: 2005-May-20
Included in the Prior Art Database: 2005-May-20
Document File: 2 page(s) / 74K

Publishing Venue

Siemens

Related People

Juergen Carstens: CONTACT

Abstract

During the DRAM (Dynamic Random Access Memory) testing, a critical write time is applied to find the faulty cells. The testing is very time consuming since the writing must be followed by a precharge after that activation command must take place. The prior art solve this problem operating the device in bank interleaved mode and as x16. It is proposed to set a special test mode that activates multiple column select lines (MSCL) at the beginning and writes the same data to all cells. An implementation is given in Figure 1. A DRAM consists of blocks of memory cells. BLs (Bit Line) are connecting the cells to the sense amplifiers (SA) on both sides of the block memory cells. The sense amplifier amplifies the signal of the cells. The CSLs connect the sense amplifiers to LDQs (Local Data Line). During the writing, the information of the LDQ will be transferred to the sense amplifier. During the normal operation, only one sense amplifier would be connected to a LDQ pair. In the proposed test mode, multiple sense amplifiers are connected to a LDQ line.

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MCSL and MSSA Test Mode

Idea: Dr. Joerg Vollrath, DE-Muenchen, Marcin Gnat, DE-Muenchen; Heinz-Joachim Neubauer, DE- muenchen

During the DRAM (Dynamic Random Access Memory) testing, a critical write time is applied to find the faulty cells. The testing is very time consuming since the writing must be followed by a precharge after that activation command must take place.

The prior art solve this problem operating the device in bank interleaved mode and as x16.

It is proposed to set a special test mode that activates multiple column select lines (MSCL) at the beginning and writes the same data to all cells.

An implementation is given in Figure 1. A DRAM consists of blocks of memory cells. BLs (Bit Line) are connecting the cells to the sense amplifiers (SA) on both sides of the block memory cells. The sense amplifier amplifies the signal of the cells. The CSLs connect the sense amplifiers to LDQs (Local Data Line). During the writing, the information of the LDQ will be transferred to the sense amplifier. During the normal operation, only one sense amplifier would be connected to a LDQ pair. In the proposed test mode, multiple sense amplifiers are connected to a LDQ line.

Alternatively, it is proposed to set a special test mode that activates multiple secondary sense amplifiers (MSSA) at the beginning and writes the same data to all cells.

An implementation is given in Figure 2. Data from blocks of memory cells are transferred from the sense amplifier via LDQ to al...