Browse Prior Art Database

Implementation of CA-Ctrl Skew Timing on HUB Chip

IP.com Disclosure Number: IPCOM000124390D
Published in the IP.com Journal: Volume 5 Issue 5 (2005-05-20)
Included in the Prior Art Database: 2005-May-20
Document File: 2 page(s) / 1M

Publishing Venue

Siemens

Related People

Juergen Carstens: CONTACT

Abstract

Today buffered DIMM hub chips are operated in normal timing mode. All ADD, CMD and Control (Ctrl) signals are launched at the same time by the Advanced Memory Buffer Chip (AMB-Chip). This timing satisfies an environment where all ADD, CMD and Control signals have the same load, i.e. the same frequency of occurrence. In an environment where the loads are not equal this timing scheme is not appropriate.

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Implementation of CA-Ctrl Skew Timing on HUB Chip

Idea: Siva RaghuRam, DE-Munich; Srdjan Djordjevic, DE-Munich

Today buffered DIMM hub chips are operated in normal timing mode. All ADD, CMD and Control (Ctrl) signals are launched at the same time by the Advanced Memory Buffer Chip (AMB-Chip). This timing satisfies an environment where all ADD, CMD and Control signals have the same load, i.e. the same frequency of occurrence. In an environment where the loads are not equal this timing scheme is not appropriate.

If the number of ranks is greater than one, the load of Control signals is less than the load of ADD and CMD signals. In those environments ADD/CMD-Control skew timing is proposed. All ADD and CMD signals are launched prior to the Control signals (ODT, CS and CKE). This adjusts the highly loaded signals compared to the other Control signals with less DRAM loads. On a multi-rank DIMM this offers the possibility to close the timing budget.

Fig. 1: DRAM U0 CA-Ctrl Skew Timing

© SIEMENS AG 2005 file: ifx_2005J50343.doc page: 1

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Fig. 2: Summary Normal vs. CA-Ctrl Skew Timing

© SIEMENS AG 2005 file: ifx_2005J50343.doc page: 2

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