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Linearity Enhanced Current-folding Output Stage for Low-voltage Current-steering DAC

IP.com Disclosure Number: IPCOM000124396D
Original Publication Date: 2005-May-20
Included in the Prior Art Database: 2005-May-20
Document File: 4 page(s) / 65K

Publishing Venue

Siemens

Related People

Juergen Carstens: CONTACT

Abstract

In advanced CMOS processes the supply voltage is progressively reduced, e.g. 1.8V in the 0.18µm technology node, 1.5V in the 0.13µm technology node, 1.2V in the 90nm technology node, etc. In such technologies the design of current-steering DACs with passive termination becomes difficult, because the available signal swing is drastically reduced. Figure 1 shows a typical implementation of a current-steering DAC with passive on-chip termination, delivering an output voltage to the following analog signal processing block, e.g. a reconstruction filter. The voltages apply to an implementation in a 0.13µm CMOS technology. Since the DAC is not able to deliver the full signal swing used in the rest of the signal processing chain, a gain is needed to accommodate the full-scale value. To achieve a certain noise-level, the input resistor R1 of the reconstruction filter must be chosen very small. This implies using very large capacitors in the filter, equivalent to an increase in area. Moreover, since the effective load seen by the DAC core is reduced from RL to the parallel combination of RL and R1, a smaller R1 results in an additional attenuation of the full-scale swing at the DAC-output, requiring more gain in the following stage, which reduces the noise margin still more. To counteract this problem, the load resistor RL can be reduced further, requiring a higher full-scale output current of the DAC-core for the same signal swing, equivalent to an increase in power consumption. Since also the operational amplifier must be designed with tighter noise specification, the design becomes more critical and the opamp will have more power consumption than with a gain of 1.

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Linearity Enhanced Current-folding Output Stage for Low-voltage Current- steering DAC

Idea: Martin Clara, AT-Villach; Wolfgang Klatzer, AT-Villach

In advanced CMOS processes the supply voltage is progressively reduced, e.g. 1.8V in the 0.18µm technology node, 1.5V in the 0.13µm technology node, 1.2V in the 90nm technology node, etc. In such technologies the design of current-steering DACs with passive termination becomes difficult, because the available signal swing is drastically reduced. Figure 1 shows a typical implementation of a current- steering DAC with passive on-chip termination, delivering an output voltage to the following analog signal processing block, e.g. a reconstruction filter. The voltages apply to an implementation in a
0.13µm CMOS technology. Since the DAC is not able to deliver the full signal swing used in the rest of the signal processing chain, a gain is needed to accommodate the full-scale value. To achieve a certain noise-level, the input resistor R1 of the reconstruction filter must be chosen very small. This implies using very large capacitors in the filter, equivalent to an increase in area. Moreover, since the effective load seen by the DAC core is reduced from RL to the parallel combination of RL and R1, a smaller R1 results in an additional attenuation of the full-scale swing at the DAC-output, requiring more gain in the following stage, which reduces the noise margin still more. To counteract this problem, the load resistor RL can be reduced further, requiring a higher full-scale output current of the DAC-core for the same signal swing, equivalent to an increase in power consumption. Since also the operational amplifier must be designed with tighter noise specification, the design becomes more critical and the opamp will have more power consumption than with a gain of 1.

Integrated current-steering D/A-converters in low-voltage CMOS processes often use an additional, higher supply voltage for the current sources only. This normally also requires additional process options (dual-gate-oxide transistors suited for the higher supply voltage). In this way the headroom for the current sources is drastically increased and therefore the full-signal swing can be delivered by the DAC. This, of course, comes at the price of higher power consumption and process cost, but is often justified for a stand-alone D/A-converter chip. Instead, in highly integrated systems special process options and additional supply voltages may not be available.

The standard circuit technique in case of limited voltage headroom is current folding, eventually combined with a regulated cascode to boost the output impedance of the current folder, see figure 2. This approach has already been used in conjunction with a current-steering DAC, although not due to limited voltage headroom, but for the implementation of a special current source calibration technique. In this design a 50% duty-cycle Return-to-Zero (RZ) coding is used, which...