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A Jitter Reduction and Clock Cycle Restoration Circuit

IP.com Disclosure Number: IPCOM000124400D
Original Publication Date: 2005-May-20
Included in the Prior Art Database: 2005-May-20
Document File: 3 page(s) / 89K

Publishing Venue

Siemens

Related People

Juergen Carstens: CONTACT

Abstract

Jitter is the deviation of the transition of a digital signal (edge) from its ideal position in time. Jitter often limits the bandwidth in data communication and limits the uppermost clock frequency. Due to the variety of jitter sources the probability density function (PDF) of jitter may be Gaussian for random jitter or non-Gaussian for deterministic jitter. Jitter is often characterized in terms of the standard deviation of the Time Interval Error (TIE) and the peak-to-peak value (PkPk). Jitter is of major concern in the design of clock recovery circuits, e. g. Delay-Locked-Loops (DLL) and Phase-Locked Loops (PLL). A typical application for a DLL is the synchronization of two or more clocks, or the synchronization of a data stream with a clock. Jitter on the input of the DLL limits the performance of the DLL itself and jitter on the output of the DLL limits the performance of circuitry that uses the synchronized clock from the DLL. The same applies for a PLL, a circuit that uses an incoming data stream to regenerate a clock from this data or to synthesize a second frequency from a first one.

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A Jitter Reduction and Clock Cycle Restoration Circuit

Idea: Dr. Thomas Nirmaier, DE-Muenchen

Jitter is the deviation of the transition of a digital signal (edge) from its ideal position in time. Jitter often limits the bandwidth in data communication and limits the uppermost clock frequency. Due to the variety of jitter sources the probability density function (PDF) of jitter may be Gaussian for random jitter or non-Gaussian for deterministic jitter. Jitter is often characterized in terms of the standard deviation σ of the Time Interval Error (TIE) and the peak-to-peak value (PkPk). Jitter is of major concern in the design of clock recovery circuits, e. g. Delay-Locked-Loops (DLL) and Phase-Locked Loops (PLL).

A typical application for a DLL is the synchronization of two or more clocks, or the synchronization of a data stream with a clock. Jitter on the input of the DLL limits the performance of the DLL itself and jitter on the output of the DLL limits the performance of circuitry that uses the synchronized clock from the DLL. The same applies for a PLL, a circuit that uses an incoming data stream to regenerate a clock from this data or to synthesize a second frequency from a first one.

Up to now large effort is put in the design and layout of DLLs and PLLs to make them less sensitive to input clock jitter and into the design of the loop filter. No circuit is known that reconstructs completely missing clock cycles.

In the following, a circuit is proposed that reduces jitter on a periodic digital signal (clock) and is able to reconstruct one or multiple completely missing clock cycles.

The circuit feeds the input clock through a tapped delay line and generates the output clock from a combination of the delayed versions of the input clock. The circuit is especially suitable to work together with a DLL or PLL in high-speed digital circuits.

The circuitry consists of

1. a tapped delay line with delays adjustable to the (average) clock cycle time,

2. processing circuitry that forms the output clock out of the delayed copies of the input clock.

The schematic of the circuitry is shown in Figure 1.

The delay line consists of k tapped delay elements with equal delay τ . This delay has to be adjusted to the clock cycle time. At the tap of the n-th delay element a delayed version of the input clock

     Φ = Φ with is tapped and fed into the processing unit. k

n -

(

 ) ( τ n t t

)

n K

 0 =

The processing unit derives the output clock from the delayed copies of the input clock.

Preferred implementations are:

1. The delayed inputs pass an analog (weighed) adde...