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Method for collecting minimal, but complete Real Address translation information in a hardware core performance trace

IP.com Disclosure Number: IPCOM000124543D
Original Publication Date: 2005-Apr-26
Included in the Prior Art Database: 2005-Apr-26
Document File: 2 page(s) / 24K

Publishing Venue

IBM

Abstract

Core performance trace consists of instruction traces of code streams running on processor cores. To generate these traces the processor has to run in single dispatch mode (one Instruction per group). In core trace mode, an image of each instruction executed in the code stream is collected by the trace hardware. The core trace data is routed on a dedicated bus to the In-Memory Tracing Facility. The purpose of the Trace Facility is to store these trace records in a predefined memory location. Associated with each instruction image are instruction and data addresses at multiple levels of translation. The challenge is to collect the translated addresses in a manner that strikes a balance between collection bandwidth and chip resources. Described is a hardware trace collection method that provides Real Address translations in a manner that saves on chip area and bandwidth, while at the same time guarantees that all Real Address translations will be captured in the resulting trace. The method saves on chip area and bandwidth by providing Real Addresses only when an ERAT (Effective to Real Address Translation) miss occurs. To ensure that no translation is omitted, the method uses ERAT invalidation.

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Method for collecting minimal, but complete Real Address translation information in a hardware core performance trace

In-Memory tracing refers to the idea of using part of the system memory to collect hardware data from system cores, buses, or caches for performance studies. The Trace Facility is the heart of the hardware trace facility. The purpose of the Trace Facility is to collect hardware trace from one of the different trace sources then store these trace records in a predefined memory location. The trace memory needs to be allocated before enable tracing. Sequential address range, behind one or more Memory Controller (MC), can be statically assigned at the IPL time or dynamically using software.

Core Performance traces is one of the input traces to the trace facility. It consists of instruction traces of code streams running on processor cores. The instruction trace image is a variable record size consisting of between two and five records, which translate into between two and eight pieces of 64-bit data. A trace, for every instruction finished execution, contains the Instruction Effective Address (IEA), the instruction PowerPC image (PPC), the Data Effective Address (DEA) if the traced instruction is a load or store, the Instruction Real Address (IRA), and the Data Real Address (DRA). To reduce the bandwidth, needed for collecting the core traces, the instruction and data real addresses are only collected when the instruction causes an Instruction Effective to Real Address Translation IERAT Instruction Effective to Real Address Translation or (DERAT) cache reloads respectively. However, in order to guarantee the presence of all address translations, the ERAT caches need to be cleared (invalidate all entries) just before start recording traces. To clear the ERAT caches in POWER5, software was used to clear or displace the current ERAT entries. One method involved the software need to w...