Browse Prior Art Database

Utilizing Internal Refresh Circuit During Fail Map Scanout

IP.com Disclosure Number: IPCOM000124558D
Original Publication Date: 2005-Apr-27
Included in the Prior Art Database: 2005-Apr-27
Document File: 3 page(s) / 33K

Publishing Venue

IBM

Abstract

A method for performing bit fail mapping during BIST test of DRAM memories and then successfully resuming test after the bit fail map data has been collected while guaranteeing that the DRAM retention interval is not violated is described.

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Utilizing Internal Refresh Circuit During Fail Map Scanout

In order to enable yield learning bit fail mapping (BFM) is required. Embedded memories are typically tested by BIST engines to minimize chip/tester equipment overhead. While the BIST is testing the memory a fail may occur and it would be desirable to pause the BIST test operations and shift the fail location data off chip to the tester equipment for bit fail mapping.

Typically, when testing an embedded DRAM core using BIST, if a fail occurs a Fail Flag indicator is generated. The ATE (automatic test equipment) recognizes the Fail Flag and provides a BFMEnable and a Clock to scan out the fail map data. While BFMEnable is asserted and the Clock input is pulsing the fail data is shifted off-chip to the ATE. The assertion of the BFMEnable typically also forces the DRAM into a non operational state (NOP state).

Due to the pause in BIST test operations while the DRAM is in a NOP state during the shift out of bit fail map information, the DRAM retention interval could be exceeded (data, stored as a charge in the DRAM capacitor cells, could leak away). When BIST testing is resumed the data in the DRAM array may have become corrupted due to the violation of the retention interval, which could lead to invalid bit fail map data as the process continues.

The solution to this issue is to enable the DRAM internal Refresh Circuitry while BFMEnable is asserted in order to avoid violating the retention specification of t...