Browse Prior Art Database

Reduced Complexity Switch

IP.com Disclosure Number: IPCOM000124601D
Original Publication Date: 2005-Apr-29
Included in the Prior Art Database: 2005-Apr-29
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Abstract

The present disclosure relates to a switching device used as the building block for a network interconnect fabric in a multiprocessor system. Some of the most important considerations when designing a switch are the queuing discipline, the effects of blocking, where the requirement is for a non-blocking switch, and arbitration, which must be fair. The implementation of these requirements can result in significant complexity and cost. The present disclosure is for a switch design that satisfies those requirements while maintaining low complexity and low cost.

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Reduced Complexity Switch

    The present disclosure provides a switch design that satisfies a number of product requirements as trade-offs are made between performance and cost. Figure 1 is a block diagram of an exemplary 4x4 switch illustrating the basic elements and structure of the invention. Following the reduced complexity goal for the switch, preferred implementations of the invention will support a fixed packet size small enough and a data path wide enough so that the data path can be realized in a single cycle. Four routers R0, R1, R2, and R3 (the notation used will be R0...R3 for short) illustrate the preferred embodiment of the invention as a partitioning of the switch logic. The I/O for the switch is through four input ports I0...I3, four output ports O0...O2 and interconnecting the routers are three dual-simplex (bidirectional) high-speed lines. The four input links are preferably serial links, so that there will be a deserializer logic block at each input port. Likewise, the four output links are preferably serial links, so that there will be a serializer logic block at each output port. Timing is extracted from the transitions in the input packet stream and synchronized with the frequency of the internal clock. Figure 1 also shows four data queues Q0...Q3, four input multiplexers m0...m3 (for simplicity, the inputs of only two of the multiplexers is shown in the figure,) and four output multiplexers M0...M3. The route that the packets take through the switch is determined by a self-routing mechanism based on a bit vector inserted by the network interconnect controller at the head of the payload.

    Assume that four inputs to the switch have been selected through the input multiplexers and latched into the head of each of the queues so that the operation can begin. The next four packets, a...