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An Integrated System and Architecture for Seamless Modeling of Functional Verification and Analysis of Simulation Results

IP.com Disclosure Number: IPCOM000124602D
Original Publication Date: 2005-Apr-29
Included in the Prior Art Database: 2005-Apr-29
Document File: 2 page(s) / 295K

Publishing Venue

IBM

Abstract

Disclosed is a functional verification system architecture and associated processes which enable development of coverage and regression models and analysis strategies independent of test generators, test program formats and simulators utilized. The disclosed integrated verification and analysis platform is based on a unified central test feature representation and a common coverage and regression modeling language and processing environment.

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An Integrated System and Architecture for Seamless Modeling of Functional Verification and Analysis of Simulation Results

There are at least three distinct tasks involved in the functional verification of complex integrated circuits such as Processors, ASICs, and SoCs. These include: (1) Test and stimulus generation, (2) Simulation, test debug and design bug analysis, and (3) Coverage modeling, coverage analysis and regression generation/optimization.

     Each of the above tasks are usually conducted in a separate platform/environment - some home grown and some from EDA vendors. There is usually no flow continuity between the above verification stages. These stages are artificially integrated via data conversion and/or model regeneration from a combination of the design source, tests, verification traces and simulation/coverage models.There is very little reuse of verification intelligence from one stage to next and among heterogenous tool flows.

     Each system and method utilized (i.e. test generator, coverage modeling environment, simulation environment, regression generation and optimization, ...) has its own interface, internal data model, modeling and control language or scripting, database, etc.. Changes and optimization in one stage can not be easily propagated to other stages due to incompatibility of languages, data models, processes and databases.

     Disclosed is an integrated verification and analysis platform architecture based on a unified central test representation and a common coverage and regression modeling language/environment as shown in Figure 1. The disclosed verification platform enables development of coverage and regression models and strategies independent of test generators, test program formats and simulators utilized.

Process and Logistics Management

Design Attributes/Configs

Sim Env. Attributes/Config

DVA Attributes & Definitions

Modeling Libs & Checkers

18

User profiles, Server Queues

Random, Det., Test benches, Regression

Test Programs

Simulation Env.

asserion/Checkers, VCD,Logs,...

4

Architectural

5

7

Signature Generator

MicroArchitectural

6

Signature Generator

Test & Verif. Env. Attributes

(DVA Repository)

8

9

Signature Analyzer

Optimizer

Signature

Test info

Repository

Model

   Model Analysis (Parse, decompose, rate, sort,...)

Regression Analysis (New, Unique & Dense tests)

10

12

Signature Repository

Regression

Coverage Signature Database

(MySQL/PHP)

Cvg & Hole

Attributes

11

13

3

Model Syntax Checker

Model Generator

2

Model Template Library

1

Model Editor/Builder

       Reports & Stats Web-based Interface/Modeling/Analysis 17

HDL, Monitors, Checkers, V.E., TestPlans

Reports & Stats

Model Entry Coverage Query,

14 15 16

Regression Query,

Figure 1: System Architecture and Functional Diagram (System Process Model)

1

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     Test programs developed for an IC (Integrated Circuit) design functional verification Fig. 1 (4) such as random tests and deterministic te...