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Decoupling Tunnel Junction Encapsulation and Interlevel Dielectric Deposition in MRAM Crosspoint Cell Architecture Disclosure Number: IPCOM000124658D
Original Publication Date: 2005-May-03
Included in the Prior Art Database: 2005-May-03
Document File: 9 page(s) / 447K

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Decoupling Tunnel Junction Encapsulation and Interlevel Dielectric Deposition in MRAM Crosspoint Cell Architecture


     Magnetic Random Access Memories (MRAM) are promising as a universal memory technology. MRAM processing involves modifying the standard Back End of Line (BEOL) processing to insert Magnetic Tunnel Junctions (MTJ). The cross-point cell (XPC) is one of the architectures pursued for MRAM. Gallagher et al disclose such architecture, where MTJs are placed at the intersection of perpendicular word and bit lines [1]. The individual bits are addressed for both Read and Write operations by selecting the bit and wordlines that intersect over the TJ. In contrast, the one transistor-one TJ (1T1J) architecture uses a select transistor for the Read operation [2]. By eliminating the select transistor, higher densities and lower cost due to the mask levels saved are claimed for the XPC but at the expense of increased parasitic and lower read access speed.

     However certain technical challenges arise from the need to insert TJs between two levels of wiring (see fig. 1). We disclose herein, the resultant problem and a solution.

TJ Encapsulation Vs ILD Deposition

     Since the TJ is inserted between two metal levels (Mn & Mn+1), the TJ is encapsulated by the Mn+1 Interlevel Dielectric (ILD). There however exist disparate requirements on the dielectrics used for TJ encapsulation and an ILD. Whereas a TJ encapsulant is required to preserve the magnetic and electric properties apart from being a diffusion barrier, the ILD for damascene metal wiring require that the interface adhesion with the lower (Mn) ILD be strong to withstand Chemical mechanical polishing (CMP) steps. Since a single material may not satisfy the dual requirements of a TJ encapsulant and ILD, an integration scheme that decouples the two is needed.

Spacer Formation

     Dielectric Spacers are widely used in modern Very Large Scale Integration (VLSI) fabrication of semi-conductor. A process known and etchback is typically used to form spacers. Fig. 3 explains this scheme, well known to those skilled in the art of material deposition and etch. A conformal dielectric is


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deposited on a vertical stud. The deposition process results is a film depth higher adjacent to a vertical structure than on top of a horizontal surface. When an anisotropic plasma based etch is performed for a time sufficient to remove material of thickness on top of horizontal surfaces, a spacer is left behind adjacent to vertical edges.

Proposed Integration Scheme

     In order to optimize encapsulation and yet not deviate much from standard ILDs used in BEOL processing, we propose a mechanism whereby a spacer is formed around MTJs. This spacer would preferably be of a material that is has superior performance is preserving MTJ properties such as Magnetoresistance (MR), TJ resistance and switching properties. The spacer can afford to have poor ILD properties such as capacitance and adhesion. Since...