Browse Prior Art Database

Horizontal Backside Crackstop

IP.com Disclosure Number: IPCOM000124669D
Original Publication Date: 2005-May-03
Included in the Prior Art Database: 2005-May-03
Document File: 4 page(s) / 57K

Publishing Venue

IBM

Abstract

This invention comprises a "crackstop" that can be fabricated as a horizontal (i.e. located in a plane parallel to the die backside) barrier structure for SOI wafers, that will act to interrupt and terminate the propagation of any crack prior to it's entering the device zone. This crackstop is easily integrated into the normal fabrication process sequence that is used to manufacture SOI wafers.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 54% of the total text.

Page 1 of 4

Horizontal Backside Crackstop

Main Idea

Background:

Die cracks originating at the backside of the silicon chip and propagating inward (toward the device region), can initiate due to the packaging bond-and-assembly (B&A) process or material configuration, and propagate during thermal cycling. This can result in module yield loss, but of greater concern, could adversely impact product reliability in the event of crack propagation through the device and wiring levels after the part is sold. Reliability stressing has identified this fail mechanism on parts that failed electrically during Deep Thermal Cycle (DTC) heat-cycling, but through SEM analysis it has also been confirmed that parts that did not fail electrically on stress may also have vestigial cracks that (for whatever reason) had not yet propagated into the integrated circuit pattern. A picture of just such a cracked part is attached below.

*

Summary of Invention:

This invention comprises a "crackstop" that can be fabricated as a horizontal (i.e. located in a plane parallel to the die backside) barrier structure for SOI wafers, that will act to interrupt and terminate the propagation of any crack prior to it's entering the device zone. This crackstop is easily integrated into the normal fabrication process sequence that is used to manufacture SOI wafers.

Description:

The invention consists of three embodiments, as shown schematically in the attachment below. In all three, the crackstop is formed on the substrate silicon prior to the deposition of the "BOx" layer which precedes the wafer bonding step that is used to create an SOI wafer. In all three embodiments, the

1

[This page contains 1 picture or other non-text object]

Page 2 of 4

crackstop is described as a WSix (tungsten silicide) refractory layer, but that should be understood to be a typical, easily integratable layer, chosen in this example for illustrative purposes. Other materials could be used as well. In the first embodiment, the horizontal crackstop consists of a simple thin film of refractory...