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Interface Structure for a Programmable Co-Processor with Tightly Coupling and System Bus Interface

IP.com Disclosure Number: IPCOM000124718D
Original Publication Date: 2005-May-04
Included in the Prior Art Database: 2005-May-04
Document File: 4 page(s) / 52K

Publishing Venue

IBM

Abstract

The proposal covers details of interfaces of a coprocessor consisting of a programmable logic array which is tightly coupled to a CPU core and has a systembus interface as well.

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Interface Structure for a Programmable Co -Processor with Tightly Coupling and System Bus Interface

Instructions are buffered and distributed to the different cores

Instructions are buffered and distributed to the different cores

Checksum

Checksum Checksum

Programmable Logic Resources (Cells, PALs, CAMs, Memory)

Programmable Logic Resources (Cells, PALs, CAMs, Memory)

Random Number Generator

Random Number Generator

Semaphores Semaphores

Semaphores

Timer

Timer

Interface Layer

Interface Layer

Interface components for Speed adaptation, Memory Access Protection

Interface components for Speed adaptation, Memory Access Protection

Softcores for different applications

Softcores for different applications

Instructions and parameters from CPU

Results to CPU

Instructions and parameters from CPU

Results to CPU

master and one slave interface to bus

Bus connects to memory, peripherals, processors and co-processors, etc.

master and one slave interface to bus

Bus connects to memory, peripherals, processors and co-processors, etc.

Bus

Bus

When connecting a coprocessor interface of a CPU core, such as the APU interface of the IBM PowerPC cores 405, and 440 to a configurable coprocessor, in many cases a speed adaptation (different clock rates of the processor and the configurable logic) is necessary. Furthermore it is desirable to implement functions which are needed with every configurable coprocessor in fixed logic, because this is cheaper than implementing these functions in every instance of a configurable coprocessor.

Furthermore, the system can be made more secure, also against design errors in the configurable corprocessor. For this reason, we describe an interface layer which isolates a configurable coprocessor from the processor unit and the system bus. In the above figure, such a coprocessor with several different functions and the interface layer is shown. The interface layer connects to the CPU and the system bus on one end and to the configurable logic array on the other.

It is drawn L-shaped to illustrate the dual interfaces to the system bus and to the CPU.

The main challenge of the interface is, that several independent functions can reside in the coprocessor which have independent flows of program control and data from and to the CPU and to external components via the bus:

1

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One interface from a (SW or HW) multithreaded Processor

One interface from a (SW or HW) multithreaded Processor

Interface Layer

Interface Layer

Semaphors

Semaphors

Soft Core 1 (e.g. Timers)

Soft Core 1 (e.g. Timers)

Programmable Logic

Programmable Logic

Checksum

Checksum

Counters

Counters

Interface Layer

Interface Layer

One interface to bus/ external memory

One interface to bus/ external memory

Part 1 of the interface layer is the CPU interface:

               440 CPU To Coprocessor

APU Interface Detail

Request not-yet available result

APU Interface Detail

Request not-yet available result

Instruction Code

Pr...