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Flash EPROM architecture reducing "on board" test time

IP.com Disclosure Number: IPCOM000124829D
Original Publication Date: 2005-Jun-20
Included in the Prior Art Database: 2005-Jun-20
Document File: 3 page(s) / 119K

Publishing Venue

Siemens

Related People

Juergen Carstens: CONTACT

Abstract

The aim of the idea is to reduce the time required to verify the correct mounting of a flash EPROM (Erasable Programmable Read Only Memory) soldered on a PCB (Printed Circuit Board). Up to now, the procedure normally adopted follows the criteria of writing all the memory location with some predefined data and than read back for the verification. This kind of approach loses in terms of efficiency when the memory size increases and in case of FLASH EPROM where the programming cycle and the erase action require a significant amount of time. The FLASH EPROMs are non-volatile memories that can be read and programmed on board by the microprocessor without the need of external programming logic. In order to be written, the entire FLASH EPROM or a part of it (sector) has to be previously fully deleted, also if only one cell is to be programmed. The chip erase or sector erase are normally very time consuming actions. It should be also considered that the FE cell programming cycle is slower (more than one CPU (Central Processing Unit) cycle needed) respect to the same operation done in the case of a RAM (Random Access Memory) type memory. Furthermore, meanwhile it is easy and fast to test the Data bus integrity, for instance using dedicated patterns with a limited number of cycles and a few memory cells involved, this is not true when the address bus integrity has to be checked. This is because, even in case of wrong connections on the address lines (short, open or stuck) the data will be placed anyway in the memory array and correctly read back. Only a full memory addressing and dedicated data pattern will be able to discover the fault.

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Flash EPROM architecture reducing "on board" test time

Idea: Paolo Illuminati, IT-L'Aquila

The aim of the idea is to reduce the time required to verify the correct mounting of a flash EPROM (Erasable Programmable Read Only Memory) soldered on a PCB (Printed Circuit Board). Up to now, the procedure normally adopted follows the criteria of writing all the memory location with some predefined data and than read back for the verification. This kind of approach loses in terms of efficiency when the memory size increases and in case of FLASH EPROM where the programming cycle and the erase action require a significant amount of time.

The FLASH EPROMs are non-volatile memories that can be read and programmed on board by the microprocessor without the need of external programming logic. In order to be written, the entire FLASH EPROM or a part of it (sector) has to be previously fully deleted, also if only one cell is to be programmed. The chip erase or sector erase are normally very time consuming actions. It should be also considered that the FE cell programming cycle is slower (more than one CPU (Central Processing Unit) cycle needed) respect to the same operation done in the case of a RAM (Random Access Memory) type memory. Furthermore, meanwhile it is easy and fast to test the Data bus integrity, for instance using dedicated patterns with a limited number of cycles and a few memory cells involved, this is not true when the address bus integrity has to be checked. This is because, even in case of wrong connections on the address lines (short, open or stuck) the data will be placed anyway in the memory array and correctly read back. Only a full memory addressing and dedicated data pattern will be able to discover the fault.

To simplify the address bus integrity test for the on board mounted FLASH EPROM, the proposal is to insert in the FLASH EPROM device a register that under test condition latches the address bus configuration in order to be read back, via data bus,...