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A Fault Tolerant Loading Mechanism of the OTP Settings

IP.com Disclosure Number: IPCOM000124836D
Original Publication Date: 2005-Jun-20
Included in the Prior Art Database: 2005-Jun-20
Document File: 2 page(s) / 43K

Publishing Venue

Siemens

Related People

Juergen Carstens: CONTACT

Abstract

The OTP (One Time Programmable) settings, which are stored into an assigned physical sector of the Flash array, can be corrupted by physical faults. However, the consistency of these setting is mandatory for the correct behavior of the device, since they are loaded during each power-up. Up to now, an OTP content mismatch check is not available in current designs. Thus any fault in the OTP setting page induces unrecoverable device misbehavior. In the following, a fault tolerant mechanism is described that is able to detect and to correct most of the faults corrupting the contents of the OTP setting. The idea is to store multiple copies of the OTP settings and some additional fault detection on the area assigned for this purpose. This is possible because the OTP settings occupy only a small part of this area in the current designs. The implementation of the proposed mechanism is software based. An overview is shown in Fig. 1. At power-up, while reading the OTP values from the array into the test registers, the software checks if the loaded OTP settings are matching the fault detection information. Therefor, the software compares the counted number of zeros to the expected number. If there is a match, then the power-up sequence can be continued. Whenever, a mismatch is detected, the OTP settings are loaded from the next mirrored OTP setting page and the check is performed again. In the last step of the procedure, an update of the PFROM content is required that describes the address of the new valid OTP setting page. If the PFROM content can't be programmed internally, then the OTP fault detection procedure starts from the originally assigned OTP setting page address at power-up.

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A Fault Tolerant Loading Mechanism of the OTP Settings

Idea: Alessandro Fin, DE-Dresden; Ifat Nitsan, DE-Dresden

The OTP (One Time Programmable) settings, which are stored into an assigned physical sector of the Flash array, can be corrupted by physical faults. However, the consistency of these setting is mandatory for the correct behavior of the device, since they are loaded during each power-up.

Up to now, an OTP content mismatch check is not available in current designs. Thus any fault in the OTP setting page induces unrecoverable device misbehavior.

In the following, a fault tolerant mechanism is described that is able to detect and to correct most of the faults corrupting the contents of the OTP setting. The idea is to store multiple copies of the OTP settings and some additional fault detection on the area assigned for this purpose. This is possible because the OTP settings occupy only a small part of this area in the current designs. The implementation of the proposed mechanism is software based. An overview is shown in Fig. 1. At power-up, while reading the OTP values from the array into the test registers, the software checks if the loaded OTP settings are matching the fault detection information. Therefor, the software compares the counted number of zeros to the expected number. If there is a match, then the power-up sequence can be continued. Whenever, a mismatch is detected, the OTP settings are loaded from the next mirrored OTP setting page and the check is performed again. In the last step of the procedure, an update of the PFROM content is required that describes the address of the new valid OTP setting page. If the PFROM content can't be programmed internally, then the OTP fault detection procedure starts from the originally assigned OTP setting page a...