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Memory Management Caching using Protection and Address Translation Caches.

IP.com Disclosure Number: IPCOM000124843D
Original Publication Date: 2005-May-10
Included in the Prior Art Database: 2005-May-10
Document File: 2 page(s) / 25K

Publishing Venue

IBM

Abstract

Disclosed is a mechanism for improving the performance of InfiniBand* Host Channel Adapter memory management by caching protection and address translation tables within the HCA. Disclosed are mechanisms for implementing such a cache, and breaking up the cache into separate independent components.

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Memory Management Caching using Protection and Address Translation Caches .

Typically the protection and address tables used by an InfiniBand* Host Channel Adapter (HCA) for memory management are stored in memory external to the HCA. IIn order to improve the efficiency of the address translation process, it is desirable to cache parts of these tables in memory internal to the HCA that can be accessed much faster. Described is a mechanism for implementing such a cache.

The HCA is required to perform two distinct functions when performing the address translation process. The first step is to perform the protection checks necessary to verify that the requested memory access is permitted. In order to perform these checks, the contents of the Protection Table (PT) entry are required. The second step is to translate the virtual address referencing the location in memory to the real address of the page that corresponds to this virtual address. For this step, the address translation table entries referenced by this protection table entry are required. In order to perform these two steps efficiently, the cache is comprised of two parts; namely, the Protection cache and the Address Translation cache.

The protection cache contains the information that is required by the HCA to perform the protection checks that are necessary before accessing memory specified by a Data Segment, RDMA packet or an atomic operation. The contents of this cache are Protection Table Entries (PTEs). These entries can also be used in the first step of the address translation process; that is the calculation of the memory region/window offset.

This protection cache may be organized in many ways, using standard caching techniques, depending on the allocation and the usage of the memory regions. It may be comprised of multiple sets where each set contains control bits and an index tag that is used to verify that the entry matches the specific Local Key (L_Key) or Remote Key (R_Key) that is being used to access the protection table entry. The set may be accessed using the low order bits of the key index as a protection cache index, although other combinations of bits could be used for this index. Multiple blocks, consisting of groups of sets may be implemented to improve the probability of locating a PTE in the cache. The number of sets and the number of blocks may either be fixed for a given implementation, or it may be configurable by initialization software.

The Index Tags may be the valid high order bits of the PT Index, or other values if a different indexing scheme is used. The valid high order bits of the PT Index are dependent on the size of the PT implemented. The Index Tag is compared with the corresponding bits in the L_Key/R_Key that is being used to access the memory r...