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Segmented Source Line Architecture of Flat Panel Display

IP.com Disclosure Number: IPCOM000124932D
Publication Date: 2005-May-13
Document File: 2 page(s) / 61K

Publishing Venue

The IP.com Prior Art Database

Abstract

Segmented Source Line Architecture of Flat Panel Display

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Segmented Source Line Architecture of Flat Panel Display

Disclosed is a method to control the source line operation, in order to reduce the power consumption rate of the electronics of a flat panel display.

Background

Currently, there is high power consumption on the source line because of a full charge up and discharge of the source data. The source line contains a large capacitive load, and the voltage amplitude of the source line is frequently changed by every image on the frame.

To address this problem, the voltage swing of the source line is reduced and a low voltage liquid crystal is used; however, this leads to poor picture quality and additional manufacturing costs.

General Description

The disclosed method uses a thin film transistor (TFT) array, which is used in various types of flat panel display products; it is composed of a matrix of the gate line and source line, with the first MOS transistors on an every conjunction node of gate/source line condensing a charge into a pixel capacitance.  The pixel capacitance is composed of the plate pixel electrode and common electrode. The disclosed method integrates the second MOS switch array, to isolate the line loading of the source line array from the identified part of the source line array. The control signal of the second MOS switch array is generated by the information of the gate line selection, and passes through the TFT array along with the gate line.

The gate lines are activated sequentially, one by one in a pre-...