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Method for a single-ended partial decoding nibble cell

IP.com Disclosure Number: IPCOM000125112D
Publication Date: 2005-May-19
Document File: 5 page(s) / 206K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a single-ended partial decoding nibble cell. Benefits include improved functionality, improved power performance, and improved cost effectiveness.

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Method for a single-ended partial decoding nibble cell

Disclosed is a method for a single-ended partial decoding nibble cell. Benefits include improved functionality, improved power performance, and improved cost effectiveness.

Background

              Conventionally, register files are designed using single-bit memory cells. A variety of bit cells are available, including:

•             Single-ended cells

•             Dual-ended cells

•             Dual-n cells

•             Latch cells

              The various cells serve different purposes. In register files/Q-files, write data is common for all the entries in single bit, regardless of the cell type used. Dual-ended cells utilize this fact and reduce the number of devices in the memory cell. However, this results in an increased number of tracks because it requires write DATAIN and write DATAIN# to write to the memory cell. In multi-ported designs, this requirement becomes a bottleneck and dictates the bit pitch of the memory cell. Dual-n cells invert the write data locally in the memory cell reducing the number of tracks but results into more devices. Conventional single-ended cells write using DATAIN, which results in more devices than dual n but lesser tracks. If compared against Dual-ended, it has more devices and lesser tracks. All these advantages of single ended cells can be further harnessed with the single ended partial decoding nibble cell. Latch cell in general are bulky so are not even considered in the study.

General description

             

              The disclosed method is a single-ended partial decoding nibble cell. The method removes the physical boundaries between the cells and merges 4-bit cells in a single cell. As the physical boundaries are removed, devices connected to write data can be shared, which reduces the number of devices and leakage paths (figure 1). Additionally, the requirement for global tracks for write data# is eliminated. Partial decoding is also done in the memory cell itself saving 2 word-line tracks/port for each 8 cells.

Advantages

              The disclosed method provides advantages, including:
•             Improved functionality due to saving area by using fewer devices

•             Improved power performance due to saving active power

•             Improved power performance due to having ¼ the number of leakage paths as the conventional solution

•             Improved power performance due to having a weaker leakage path on both sides of the memory cell

•             Improved power performance due to having ¼ the number of gate cap on write bit lines

•             Improved power performance due to having smaller interconnect caps on all the bit lines

•             Improved cost effectiveness due to eliminating the tracks required for the global bit lines

Detailed description

                            The disclosed method is a single-ended partial decoding nibble cell. The method enables partial wordline decoding inside the memory cell. Four write wordlines are...