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Method for a low-power low-latency voltage-mode driver with equalization

IP.com Disclosure Number: IPCOM000125118D
Publication Date: 2005-May-19
Document File: 7 page(s) / 492K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a low-power low-latency voltage-mode driver with equalization. Benefits include improved functionality and improved performance.

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Method for a low-power low-latency voltage-mode driver with equalization

Disclosed is a method for a low-power low-latency voltage-mode driver with equalization. Benefits include improved functionality and improved performance.

Background

              Conventionally, voltage-mode drivers have been the preferred choice of transmitter design for front-side bus applications for many years. They are popular because of their simple design and low power consumption. However, they have shortfalls that prevent them from being used in high-speed input/output (I/O) solutions, including the following:

•             High susceptibility to Ldi/dt noise and simultaneous switching output (SSO) noise in single ended designs

•             Poor common mode rejection (CMRR)

•             Poor driver linearity due to inherent non-linear behavior of MOS devices

              To obtain the same swing at the pad, a voltage-mode driver requires half the current used with a current mode driver to be drawn from the supply. If designed correctly, the voltage mode driver provides inherently low power dissipation (see Figure 1).

              Cursor is the buffered (delayed) version of the current data bit. The post-cursor is the delayed and inverted (negative coefficient) version of the same data bit.

              Non-linearity is defined as the actual deviation from ideal resistance measured at 600 mV swing when pad voltage is swept through its range.

General description

              The disclosed method is a low-power low-latency voltage-mode driver with equalization.

The technology is applicable in all high-speed I/O interfaces.

              The key elements of the disclosed method include:

•             Modular architecture

•             Slew rate control, Rout control, and the predriver integrated into one block

•             Tx equalization controlled by differential pair slices

•             Implemented with TAP finite-impulse-response (FIR) transmit (Tx) pre-emphasis or Tx equalization

•             Predriver with a fan-out of one driver cell

•             Slew rate weight selected by a multiplexer

•             Multiplexer that controls the rise and fall times of the predriver signal and the driven output waveforms

•             Receive (Rx) termination of 2Z0 or ground

•             Semiconductor devices share a poly-resistor

•             TAPs signals converted by high-speed multiplexer to the full data rate when equalizer processing is complete

Advantages

              The disclosed method provides advantages, including:
•             Improved functionality due to providing a simplified predriver design

•             Improved functionality due to providing equalization with the voltage-mode driver

•             Improved functionality due to providing a differential voltage-mode driver that includes multi-TAP transmit pre-emphasis at 8-10 Gb/s operation

•             Improved functionality due to providing a low-power modular architecture

•             Improved functionality due to providing p...