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Method for effectively using the through-silicon via-interconnect area for clock distribution in a 3-D multistrata IC

IP.com Disclosure Number: IPCOM000125119D
Publication Date: 2005-May-19
Document File: 5 page(s) / 99K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for using the through-silicon via-interconnect area for clock distribution in a three-dimensional (3-D) multistrata integrated circuit (IC). Benefits include improved functionality, improved performance, improved power performance, improved thermal performance, reduced die area, and improved design flexibility.

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Method for effectively using the through-silicon via-interconnect area for clock distribution in a 3-D multistrata IC

Disclosed is a method for using the through-silicon via-interconnect area for clock distribution in a three-dimensional (3-D) multistrata integrated circuit (IC). Benefits include improved functionality, improved performance, improved power performance, improved thermal performance, reduced die area, and improved design flexibility.

Background

      The semiconductor industry is developing a 3-D wafer or die-stacking technology that bonds two or more die together to form a connected IC structure. The dice are connected with metal vias at the die-die interfaces. To utilize conventional methods of component assembly, a heatsink is attached to the bulk of the #1 (thick) die. The power input/output (I/O) connections to the package or circuit board are made with existing controlled collapse chip connect (C4) bump technology attached to the bulk of the #2 (thin) die (or die nearest the package for stacks>2 die). Through-silicon vias pass (TSVs) through the second (and subsequent die for stacks > 2) die and connect to the metal die-to-die interface (see Figure 1).

      Because the through-silicon vias pass through the active silicon area of the second die, sufficient area must be allocated in the circuitry to permit the TSVs. These vias are typically large (>10X) compared to the minimum design rules of the process due to power delivery requirements. They dictate approximately 1 TSV per C4 bump minimum. To keep cost and processing complexity low, a single layer of backside metal is advantageous.

      The C4 bumps are usually arranged in a widely spaced uniform pattern across an entire two-dimensional die, enabling a high number of uniform power and ground connections to the top layer metal. Additional layers of metal are typically used to create a semi-uniform power grid to supply power to the active silicon layers (see Figure 2). This array opens up “white space” on the #2 die between the TSV’s that cannot always be effectively utilized by the non-clock circuitry.

      Conventional high-frequency IC designs use an internal clock distribution grid network. The locations for the grid drivers are predetermined early in the design implementation. Clock stripes run either vertically or horizontally along the length of the die and are approximately evenly spaced. These stripes contain the large number (1000+) inverters and their interconnects. They comprise the preglobal clock network (phased-lock loop output to the die center) and the global clock grid drivers that drive the interlaced top-level metal clock grid. Local clock drivers within each processor block connect to this metal grid to complete the three-level distribution. The circuitry within these stripes act as boundaries between chip components by blocking a large percentage of the silicon and lower metal levels (see Figure 3).

Description

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