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Method for on-die TR lock time and BER measurement device for a serializer/deserializer

IP.com Disclosure Number: IPCOM000125121D
Publication Date: 2005-May-19
Document File: 5 page(s) / 56K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for on-die time recovery (TR), also called (CR)-clock recovery lock time and bit-error rate (BER) measurement device for a serializer/deserializer. Benefits include improved functionality, an improved test environment, improved performance and mainly ease of use.

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Method for on-die TR lock time and BER measurement device for a serializer/deserializer

Disclosed is a method for on-die time recovery (TR), also called (CR)-clock recovery lock time and bit-error rate (BER) measurement device for a serializer/deserializer. Benefits include improved functionality, an improved test environment, improved performance and mainly ease of use.

Background

              High-speed differential busses that are becoming popular and will be more so in the future present testing issues due to high wire speeds The required test equipment is prohibitively expensive and is not available to engineers in adequate quantities. Additionally, the precision of the test-equipment is approximately the same as the device under test (DUT).

              Specifically, measuring the BER and the TR lock time is difficult. Laboratory setup to perform the measurements requires the development of special printed circuit boards (PCBs), field programmable gate array hardware and control software, and very expensive test equipment.

              In addition, production testing on automated test equipment (ATE) is very difficult. ATEs that operate at the required speeds are not available. Modules that provide limited possibilities are very expensive, have limited availability, and are very complicated in terms of developing a production test program. The long development cycle requires a large investment of time and money.

                            Embedding testability features into chips is becoming increasingly popular as chip complexity and frequency rise and cost per gate shrinks.

              The BER is defined as the number of erroneous bits divided by the number of bits transmitted. Measurement of the test time outside the DUT is important, such as in the test port control software that initiates the start signal assertion. This process is imprecise due to the inherent latencies in the test host.

General description

              The disclosed method embeds a BER measurement and TR lock-time meter into application logic. The key elements of the method include:

•             Small configurable buffer for holding the symbols to be transmitted (4 10-bit symbols)

•             2 counters, one for errors and one for lock-time (12 bit each in our implementation)

•             4-bit finite state machine (FSM) and some control logic

•             Self-loopback capabilities on board or on die

Advantages

              The disclosed method provides advantages, including:

•             Improved functionality due to providing a cost-effective solution for the BER and TR mechanism lock time for high-speed communication specifications

•             Improved test environment due to providing a production environment solution for testing BER and TR mechanism lock time

•             Improved performance due to providing BER and TR mechanism lock-time functionality with a very small addition to the chip gate count.

Detailed description

              The disclosed method uses an existi...