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Method for multiple-pulse wordlines for improved SRAM cell read/write stability

IP.com Disclosure Number: IPCOM000125131D
Publication Date: 2005-May-19
Document File: 4 page(s) / 196K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for multiple-pulse wordlines for improved static random access memory (SRAM) cell read/write stability. Benefits include improved functionality, improved performance, and improved cost effectiveness.

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Method for multiple-pulse wordlines for improved SRAM cell read/write stability

Disclosed is a method for multiple-pulse wordlines for improved static random access memory (SRAM) cell read/write stability. Benefits include improved functionality, improved performance, and improved cost effectiveness.

Background

              Cell flipping at a read operation is a dynamic event. When a wordline (WL) starts ramping up, SRAM cell nodes start moving in opposition to flip the unstable cell. At the same time, the bitline (BL) connected to the “0” side of the cell starts drooping. This discharge improves the cell ratio. The pass device is weaker because its drain-side voltage, Vds, is slightly smaller than the control circuit voltage, VCC. Its threshold voltage, Vth, is larger due to a lower drain-induced-barrier-lowering (DIBL) effect.

              If the WL is kept high long enough, the on-going droop may not be sufficient to prevent the cell from toggling and the cell eventually looses its contents. If the WL is kept ON for a short period of time, (tens of picoseconds), the cell does not flip because it does not have enough time to drive its nodes in opposite directions. However, this short time may not be sufficient to read or to write the cell.

      A conventional SRAM bank is comprised of M rows and N columns of memory cells. The bank has four main components (see Figure 1):

•             Row decoder

•             Timer

•             Input/output (I/O)

•             Memory array

      Note: Bits of the same memory word are separated from each other to simplify I/O design.

      In this example, a group of 8 columns share a single (large) sense-amplifier. An 8-to-1 multiplexer (MUX) is used to connect one column to the sense amplifier (SA) during a read operation. Another 8-to-1 MUX is used to connect the selected column to a write driver during a write operation. On a read operation, the following steps are performed:

1.           Charge the bitlines to full-VCC during the precharge phase of the clock (PCH# is low) using positive-channel metal oxide semiconductor (PMOS) devices.

2.           During the evaluate phase, turn OFF the precharge and enable one WL based on row decoding by driving the selected WL to VCC using the WL driver. At the same time, use the column select circuit (see Figure 2) to connect one of every eight bit-line pairs to the corresponding SA (see Figure 3).

3.           Based on the cell content, either “bli” or “bli#” starts dropping below VCC, developing a small differential voltage on the bit-line pairs. T...