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A Single-Ended Continuous Time Equalized Driver

IP.com Disclosure Number: IPCOM000125141D
Publication Date: 2005-May-20
Document File: 2 page(s) / 84K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a line driver that combines a voltage-mode data driver with a current-mode circuit to implement continuous time transmit equalization. Benefits include a larger receive signal swing and a better signal-to-noise ratio.

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A Single-Ended Continuous Time Equalized Driver

Disclosed is a method for a line driver that combines a voltage-mode data driver with a current-mode circuit to implement continuous time transmit equalization. Benefits include a larger receive signal swing and a better signal-to-noise ratio.

Background

Equalization of voltage-mode drivers is difficult to implement with the same type of calibration used for impedance compensation. When trying to attain high resolution for impedance and equalization tuning, the number of driver segments increases geometrically; this increases the pad capacitance. This problem is currently solved by changing the entire driver to a current-mode structure; however, this typically consumes twice the output stage power of a voltage mode design. The equalized data signal must be de-emphasized from the unequalized case to stay within driver circuit swing limitations, but this limits the receive signal-to-noise ratio.

General Description

The disclosed method consists of three main blocks: a filter circuit, a main driver, and an equalization driver. As shown in Figure 1, the main driver is a traditional 50 ohm push-pull circuit, divided into multiple legs for impedance control. The process, voltage, and temperature variations require five bits of resolution for typical applications (i.e. 32 driver segments). The legs are connected in parallel to produce a 50ohm (or any other) driver impedance.

The equalization driver consists of a current-mode driver. A potential implementation is shown in Figure 1, where an NMOS current-source is used. The equalization driver is controlled by a continuous time filter circuit and bias circuit. The filter generates an analog equaliza...