Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Phase-Roll Counter Synchronization Methodology

IP.com Disclosure Number: IPCOM000125318D
Original Publication Date: 2005-Jun-20
Included in the Prior Art Database: 2005-Jun-20
Document File: 3 page(s) / 356K

Publishing Venue

Siemens

Related People

Juergen Carstens: CONTACT

Abstract

The objective of this idea is to synchronize 2 distinct clock sources for the purpose of avoiding clock slip between the two asynchronous clocks. This will result in better quality since data will be neither lost nor inserted to fill clock slips. Two distinct clock sources exist for separate serial data lines, each with their own frame synchronization pulse signal indicating the start of a frame of data. Assuming one clock is fixed (external network) and the other is frequency controllable (internal) we can implement some algorithms to control the frequency of the internal clock to match it to the external clock within a small amount of deviation per frame. Two separate problems are to be dealt with: on the one hand the methodology for implementing a control system to provide synchronization data necessary to allow synchronization; and on the other hand a methodology for controlling the internal clock based upon inputs from the control system to ensure synchronization within an allowable tolerance. The control system, shown in figure 1, may consist of a frequency controllable clock source for the internal clock, a counter register, and a master control module that controls the processing of these elements. The counter register is increased with every tick of the internal clock. With the occurrence of a frame sync pulse from the external clock source, the counter register is reset. The value at time of reset is stored in the phase roll register (figure 2, left) which is readable by the master control module (figure 2, right). In this manner, the master control module may read the number of clock ticks elapsed between frame syncs from the external clock and the internal clock. In other words, the phase roll register contains the number of clock ticks between the 2 frame synch pulses.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 52% of the total text.

Page 1 of 3

S

Phase-Roll Counter Synchronization Methodology

Idea: Curtis Pastor, US-Dallas, Texas; Klaus Fosmark, US-Dallas, Texas; Ken Lauffenberger, US-

Dallas, Texas; Mark Mead, US-Dallas, Texas; Mark Gladden, US-Dallas, Texas

The objective of this idea is to synchronize 2 distinct clock sources for the purpose of avoiding clock slip between the two asynchronous clocks. This will result in better quality since data will be neither lost nor inserted to fill clock slips.

Two distinct clock sources exist for separate serial data lines, each with their own frame synchronization pulse signal indicating the start of a frame of data. Assuming one clock is fixed (external network) and the other is frequency controllable (internal) we can implement some algorithms to control the frequency of the internal clock to match it to the external clock within a small amount of deviation per frame. Two separate problems are to be dealt with: on the one hand the methodology for implementing a control system to provide synchronization data necessary to allow synchronization; and on the other hand a methodology for controlling the internal clock based upon inputs from the control system to ensure synchronization within an allowable tolerance.

The control system, shown in figure 1, may consist of a frequency controllable clock source for the internal clock, a counter register, and a master control module that controls the processing of these elements.

The counter register is increased with every tick of the internal clock. With the occurrence of a frame sync pulse from the external clock source, the counter register is reset. The value at time of reset is stored in the phase roll register (figure 2, left) which is readable by the master control module (figure 2, right). In this manner, the master control module may read the number of clock ticks elapsed between frame syncs from the external clock and the internal clock. In other words, the phase roll register contains the number of clock ticks between the 2 frame synch pulses....