Browse Prior Art Database

Fusable DDFBGA substrate

IP.com Disclosure Number: IPCOM000125337D
Original Publication Date: 2005-Jun-20
Included in the Prior Art Database: 2005-Jun-20
Document File: 2 page(s) / 232K

Publishing Venue

Siemens

Related People

Juergen Carstens: CONTACT

Abstract

Electrical performance is becoming a limiting factor in high-speed high-capacity memory modules (DDR2 (Double Data Rate) and higher). When using dual-die stacked FBGA (Fine-pitch Ball Grid Array) packages as building components in a DDR2 module, there are 6 command signals (CS; CKE; ODT) routed separately to each die of the stack (point to point), and all other signals are routed to both dies (point to two point connection). This implies a difference in pin capacitances between command (CTRL) and address (CA) pins in DDFBGA (Dual Die FBGA) Faceup/Faceup packages and causes timing problems for FBDIMM (Fully Buffered Dual-In-Line Memory Module) applications. For systems with such a big loading difference between CTRL and CA signals, separate CTRL and CA bus control can be implemented (improving setup/hold timings). This implies long development time and incompatibility with many available systems at the market. The other possible solution is to compensate for the loading at module level. For FBDIMMs this is not possible due to the very dense module design.

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Fusable DDFBGA substrate

Idea: Dr. Minka Gospodinova Daltcheva, DE-Muenchen; Srdjan Djordjevic, DE-Muenchen; Dr.

Jochen Thomas, DE-Muenchen; Harry Huebert, DE-Muenchen

Electrical performance is becoming a limiting factor in high-speed high-capacity memory modules (DDR2 (Double Data Rate) and higher).

When using dual-die stacked FBGA (Fine-pitch Ball Grid Array) packages as building components in a DDR2 module, there are 6 command signals (CS; CKE; ODT) routed separately to each die of the stack (point to point), and all other signals are routed to both dies (point to two point connection). This implies a difference in pin capacitances between command (CTRL) and address (CA) pins in DDFBGA (Dual Die FBGA) Faceup/Faceup packages and causes timing problems for FBDIMM (Fully Buffered Dual-In-Line Memory Module) applications.

For systems with such a big loading difference between CTRL and CA signals, separate CTRL and CA bus control can be implemented (improving setup/hold timings). This implies long development time and incompatibility with many available systems at the market.

The other possible solution is to compensate for the loading at module level. For FBDIMMs this is not possible due to the very dense module design.

On package level, there is a possibility for a FBDIMM-dedicated DDFBGA substrate design, which is not only causing higher time to market and development costs, but also logistics problems.

The proposed solution is to design one DDFBGA substrate having the option to switch between RDIMM application (where the loading mismatch is not so critical), and FBDIMM application (with matching the loads on CA and CTRL pins).

The basic idea is to dedicate copper surfaces on DDFBGA substrate connected both to the CTRL signal and to a power supply plane. Depending on the application, the respective connection is fused (e.g. by laser cut) and the surface is therefore connected to the needed signal.

The basic principle is shown in Fig. 1. The substrates f...