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Area Efficient Miller Compensation Scheme for Low Noise Reference Buffers Employing Large Miller Capacitors

IP.com Disclosure Number: IPCOM000125367D
Original Publication Date: 2005-Jun-20
Included in the Prior Art Database: 2005-Jun-20
Document File: 3 page(s) / 64K

Publishing Venue

Siemens

Related People

Juergen Carstens: CONTACT

Abstract

Key building blocks in mixed-signal chips are operational amplifiers. Especially the Miller compensated operational amplifier is very often used. Figure 1 shows such a standard two-stage Miller compensated operational amplifier with the Miller capacitor CM and the nulling resistor RM. A special application of such an amplifier is low-noise reference buffering with large capacitive loading, possibly driving a reference voltage off-chip. Often such buffers are not required to have high bandwidth, whereas the input noise occasionally has to be very low. This implies that the transconductance of the first stage (gm1) has to be quite large, because the input reflected noise for a MOS (Metal Oxide Semiconductor) input stage is approximately (neglecting the second stage) given by

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Area Efficient Miller Compensation Scheme for Low Noise Reference Buffers Employing Large Miller Capacitors

Idea: Martin Clara, AT-Villach; Wolfgang Klatzer, AT-Villach

Key building blocks in mixed-signal chips are operational amplifiers. Especially the Miller compensated operational amplifier is very often used. Figure 1 shows such a standard two-stage Miller compensated operational amplifier with the Miller capacitor CM and the nulling resistor RM.

A special application of such an amplifier is low-noise reference buffering with large capacitive loading, possibly driving a reference voltage off-chip. Often such buffers are not required to have high bandwidth, whereas the input noise occasionally has to be very low. This implies that the transconductance of the first stage (gm1) has to be quite large, because the input reflected noise for a MOS (Metal Oxide Semiconductor) input stage is approximately (neglecting the second stage) given by

1

v ⋅

  2 in , n gm

   kT 8 2

≈ (1)

On the other hand, the so-called "second-pole" frequency of the amplifier of figure 1 is approximately given by

L

3

     2 pole C gm f 2 ≈

π (2)

For stability reasons, the open-loop unity Gain-Bandwidth (GBW) of the amplifier has to be smaller by a certain factor (2...4) than the 2nd pole frequency fpole2. The GBW of the amplifier can be approximately expressed as:

C

2

       gm GBW 2 ≈

π (3)

In the case of a low-noise application gm1 is large (equation 1). Especially when the load capacitance CL is very large, the Miller capacitor CC takes on large values. According to (2), in order to reduce CC, the transconductance of the 2nd stage gm2 can be made larger, although making gm2 larger than needed increases the power consumption of the operational amplifier, especially for very large CL.

The most effective (largest capacitance per unit area) capacitor in integrated circuits is the MOS capacitor in strong inversion. However, if the output voltage is in the range of the gate voltage of MOUT,

strong inversion cannot be guaranteed (risk of instability).

Conventional solutions implement a large Miller capacitor with a different capacitor type (Poly-Poly, Poly-Metal, Metal-Metal, etc.), all of that generally have a much lower capacitance per unit area. This leads to a large area overhead for the reference buffer. By pushing the second-pole fpole2 to higher frequencies, the Miller capacitor can be decreased and chip area saved. However, this requires increasing gm2 and thus an increase in power consumption.

The circuit of figure 2 does not need the use of a nulling resistor and shows much better PSRR (Power Supply Rejection Ratio) than the standard Miller-opamp (Operational Amplifier) (one reason for its existence). Also, the source follower MS provides a level shift via its gate-source voltage vGS. This level shift...