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RDIMM CMD-ADR Post-Register Topology for High Data Rates

IP.com Disclosure Number: IPCOM000125371D
Original Publication Date: 2005-Jun-20
Included in the Prior Art Database: 2005-Jun-20
Document File: 4 page(s) / 2M

Publishing Venue

Siemens

Related People

Juergen Carstens: CONTACT

Abstract

Memory modules operate with Data (DQ and DQs), Clock (Clk) and Command Address (CA) Signals. The Data Signals occur with less loading compared to the Clock and Command Address Signals, because the Data Signals are point-to-point or point-to-two/four-point signals. The memory controller has to drive one load for each bank on a single DQ line, but it has to drive all the CA and Clk Input Signals of all the banks (or DRAMs on the memory module). There can be 9, 18, 36, 72 … loads on a single memory module. To reduce the CA and Clk loading, Registered Modules are designed. In Registered Modules (RDIMM), a PLL is used to drive one single Clock Signal to 10 Clock Signals and a register is used to drive the CA Signals. This re-driving of the Clock and CA Signals reduces the load on Clk and CA: The memory controller drives only the PLL and the register inputs, but the PLL and the register re-drive a greater number of loads (9, 18, 36 …). Re-driving of Clk and CA Signals allows the controller to run faster, which means the register should be fast enough to transfer the Address and Command Signals to the DRAM for every clock cycle. A fast register means small tPD (delay) with good signal integrity.

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RDIMM CMD-ADR Post-Register Topology for High Data Rates

Idea: Dr. Abdallah Bacha, DE-Muenchen; Simon Muff, DE-Muenchen; Siva Raghuram, DE-

Muenchen

Memory modules operate with Data (DQ and DQs), Clock (Clk) and Command Address (CA) Signals. The Data Signals occur with less loading compared to the Clock and Command Address Signals, because the Data Signals are point-to-point or point-to-two/four-point signals. The memory controller has to drive one load for each bank on a single DQ line, but it has to drive all the CA and Clk Input Signals of all the banks (or DRAMs on the memory module). There can be 9, 18, 36, 72 ... loads on a single memory module. To reduce the CA and Clk loading, Registered Modules are designed.

In Registered Modules (RDIMM), a PLL is used to drive one single Clock Signal to 10 Clock Signals and a register is used to drive the CA Signals. This re-driving of the Clock and CA Signals reduces the load on Clk and CA: The memory controller drives only the PLL and the register inputs, but the PLL and the register re-drive a greater number of loads (9, 18, 36 ...). Re-driving of Clk and CA Signals allows the controller to run faster, which means the register should be fast enough to transfer the Address and Command Signals to the DRAM for every clock cycle. A fast register means small tPD (delay) with good signal integrity.

To get Registered Modules functional, it is important to have a positive margin for the post-register timing. When the module speed increases, it gets more difficult to get a positive margin for the post- register timing, because the clock cycle will decrease. Besides this, more critical parameters which affect the Timing Budget are the tPD and the tNetdelay:

The tPD is the minimum time needed by the signal to exit the register. It is the intrinsic delay which depends especially on the technology used. It is measured from the rising edge of the register clock input to the register output into a register test load of 30pF t...