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Loop-back Test for Bidirectional Input/Output Circuitry of Electrical Devices Using a Low-speed External Test Equipment

IP.com Disclosure Number: IPCOM000125372D
Original Publication Date: 2005-Jun-20
Included in the Prior Art Database: 2005-Jun-20
Document File: 3 page(s) / 319K

Publishing Venue

Siemens

Related People

Juergen Carstens: CONTACT

Abstract

For future DDR (Double Data Rate) electronic devices the operation frequency may approach operation frequencies of 1GHz or more, corresponding to a data rate of 2 Gb/s/pin. Hence the timing parameters of the external data interface will be very demanding, for design as well as for test. The relevant timing parameters are the input setup/hold time of the DQ (Data Bus) data pins, referred to their associate write data clock, a signal which is commonly called WDQS (Write DQS), and the output skew timing, relating the output data edges to their associated RDQS (Read DQS) read clock. The following problems occur: 1) It is not trivial and expensive to achieve the required timing accuracy. 2) The test equipment has to sample the output data taking into account the phase of RDQS ("source synchronous" sampling). In order to overcome the problems described above when using external test equipment for high speed interface timing parameter measurements, there exists a method for testing the IO (Input Output) timing parameters in a so-called loop-back approach (IO BIST- Input Output Built In Self Test). Examples of state-of-the-art loop-back solutions are shown in Fig. 1 and Fig. 2. Figure 1 shows schematically the internal IO loop-back BIST. All pins are assumed to be bidirectional. For each pin, the OCD (Off-Chip Driver) output is looped back via the pad to the receiver of the same pin. If the SCLK (clock to drive the DQS signal off-chip) is delayed by the time tS with regard to the DCLK (Clock to drive the data off-chip), the setup time of the input receiver is tS, thus enabling the test of the receiver setup time and, at the same time, the OCD output skew time late DQ/early RDQS. If the DCLK is delayed by the time tH with regard to the SCLK, the hold time of the input receiver is tH, thus enabling the test of the receiver hold time and, at the same time, the OCD output skew time early DQ/late RDQS. The disadvantage of this solution is that a critical high-speed test is not possible due to the high amplitude from the non-terminated OCD's.

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Loop-back Test for Bidirectional Input/Output Circuitry of Electrical Devices Using a Low-speed External Test Equipment

Idea: Dr. Wolfgang Spirkl, DE-Muenchen

For future DDR (Double Data Rate) electronic devices the operation frequency may approach operation frequencies of 1GHz or more, corresponding to a data rate of 2 Gb/s/pin. Hence the timing parameters of the external data interface will be very demanding, for design as well as for test. The relevant timing parameters are the input setup/hold time of the DQ (Data Bus) data pins, referred to their associate write data clock, a signal which is commonly called WDQS (Write DQS), and the output skew timing, relating the output data edges to their associated RDQS (Read DQS) read clock. The following problems occur: 1) It is not trivial and expensive to achieve the required timing accuracy. 2) The test equipment has to sample the output data taking into account the phase of RDQS ("source synchronous" sampling).

In order to overcome the problems described above when using external test equipment for high speed interface timing parameter measurements, there exists a method for testing the IO (Input Output) timing parameters in a so-called loop-back approach (IO BIST- Input Output Built In Self Test).

Examples of state-of-the-art loop-back solutions are shown in Fig. 1 and Fig. 2.

Figure 1 shows schematically the internal IO loop-back BIST. All pins are assumed to be bidirectional. For each pin, the OCD (Off-Chip Driver) output is looped back via the pad to the receiver of the same pin. If the SCLK (clock to drive the DQS signal off-chip) is delayed by the time tS with regard to the DCLK (Clock to drive the data off-chip), the setup time of the input receiver is tS, thus enabling the test of the receiver setup time and, at the same time, the OCD output skew time late DQ/early RDQS. If the DCLK is delayed by the time tH with regard to the SCLK, the hold time of the input receiver is tH, thus enabling the test of the receiver hold time and, at the same time, the OCD output skew time early DQ/late RDQS. The disadvantage of this solution is that a critical high-speed test is not possible due to the high amplitude from the non-terminated OCD's.

Figure 2 shows the external IO loop-back BIST. Here, the test loop covers also the wires from the OCD pad to the ball and from the ball to the receiver pad. An external load may be used. In contrast to the internal variant, only half of the data pins are used for output. The other half for input, e.g. the DQ0 is externally connected to DQ1, DQ2, DQ3 etc. The disadvantage of this solution is that bidirectional pins have to be split in input and output signals, a fully parallel test is not possible. Furthermore, it is very difficult to find a useful connection scheme for devices with a single bi-directional DQS signal. As can be seen from Fig. 2, separate WDQS/RDQS signals are needed.

It is proposed to use an internal loop-back, supported by an exter...