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Method and Apparatus for Input/Output Port with Directional Filter

IP.com Disclosure Number: IPCOM000125545D
Original Publication Date: 2005-Jun-07
Included in the Prior Art Database: 2005-Jun-07
Document File: 5 page(s) / 98K

Publishing Venue

IBM

Abstract

Input/Output port capable of passing high frequency signals in out and low frequency signals in. This port can operate full duplex when the port would normally operate in a simplex mode.

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Method and Apparatus for Input /Output Port with Directional Filter

With pin count limitations and the need to test internal clocks, a bidirectional input/output (I/O) port is described where the output information is different from the input information. The directional input/output port of an integrated circuit used to pass AC information out and DC information in.

     The method disclosed takes advantage of the ability to easily filter a clock signal using a low pass filter (LPF) and a capacitor to isolate the clock output from the DC input. Figure 1 describes the topology of the DC blocking capacitor, and LPF functions in the I/O block. Typically the LPF is implemented using resistor and capacitor components . The pull-up resistor provides a logic "1" DC bias in this case, but could be replaced with a pull-down resistor to provide a logic "0" bias.

     An example of this application is to output a test clock on a pin that is normally used as a digital input pin. In this case, the digital input pin is normally used for configuration and is held at logic "0" or logic "1".

     Special electrostatic discharge (ESD) structures are required to allow the I/O pin to operate above Vdd and below Vss. Typically , the ESD protection structures are diodes in series to clamp the input voltage to a maximum above Vdd or a minimum below Vss.

     Normally, dedicated pins are used or shared with a dedicated function; in this example, both functions, clock out and digital input, are functional at the same time.

     Figure 2 indicates voltage at the I/O pin. For a period of time, the DC voltage at the I/O pin is Vdd. Then, a switch gates an impedance c...