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Method of System Level Topology Management for Unrouted and Routed Packages

IP.com Disclosure Number: IPCOM000125546D
Original Publication Date: 2005-Jun-07
Included in the Prior Art Database: 2005-Jun-07
Document File: 7 page(s) / 101K

Publishing Venue

IBM

Abstract

One area of particular importance in the development of server products is high speed interconnects and packaging. This area is known as Signal Integrity (SI). SI engineers focus on designing packages and interconnects for reliable high speed signal propagation. Software tools are used by SI engineers to analyze and optimize designs prior to manufacturing actual hardware. In this manner, designs can be quickly updated and analyzed for delay and noise margins. This pre-hardware analysis of the design reduces the product development cycle time and the number of versions of hardware that might be necessary. One such software tool methodology involves topology rule writing and checking while the hardware is going through physical design. At a high level, the new methodology generates the stitched system nets by reading in extracted data from Physical Design (PD). A topology checking tool then checks these system level stitched nets against user defined rules. A report is created listing which nets match or have fail to match any of the wiring rules. Nets that have successfully matched will also have their properties noted in the feedback file which is then fed back into the PD tool. The topology checking tool provides net topology information for completely wired, partially wired or unwired nets. This enables maximum flexibility for use in early analysis through final PD design verification. The topology checking tool can be used on a single package with a single set of rules, or more importantly, it can be used to apply constraints from a single set of rules across many packages.

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Method of System Level Topology Management for Unrouted and Routed Packages

IBM* eServers* are very complex systems containing many cards, boards, cables, and chips. In order to ensure proper function and performance, the systems are designed to very tight electrical tolerances. All nets are designed and analyzed to ensure proper function and performance of the computer. These nets include both on package nets and system level nets. For example, system level nets may cross many different package boundaries within the system. One typical multiple package example begins with driver on a chip - last metal - module - socket - card - connector - backplane - connector - card - socket - module - last metal - receiver on a chip. The design of these nets include much analysis to determine proper length, placement, and routing for proper function. The analysis is complicated by the many packages that the net may span. In addition, there are 100 attributes per net that must be managed in order to enable proper wire placement and routing. This invention provides an efficient and effective method for managing the many complexities involved in system level analysis and topology management.

     Currently there are no available tools on the market that address the complexities of managing system level nets across package boundaries. Due to this limitation, it is typical for engineers to write different topology rules for each package and then manually manage these in a spreadsheet or on a sheet of paper. Then circuit simulation decks are manually written and used for analysis. Based upon these simulation results, the router topology rules are then manually updated for these nets.

     Cadence** does have a tool called Constraint Manager (CM). CM enables a user of Cadence Allegro** Physical Design Tools to extract their data and manage the net in spreadsheet fashion within the Cadence tool suite on a per package basis. CM cannot handle system level rules and topology management because CM can only handle one package at a time - not an entire system. Our invention handles system level nets. CM cannot use estimation to handle unwired nets or portions of nets to support downstream timing analysis. Our invention uses estimation to enable analysis of unwired nets to continue, thus enabling early timing analysis. CM cannot handle wildcarding in the topology rules, thus forcing the engineer to write a rule per individual net. Our invention supports wildcarding, thus enabling the engineer to write a single rule for groups of nets. This is a huge productivity saving. In addition, the rules used in the Cadence methodology are the constraints that are fed to the router and are stored in the design file. Therefore, it is difficult to track version control on the rules, constraints and the design itself. In the invention presented here, we have separated the design and the rules into separate files, thus enabling engineers to work independently on the physical design a...