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Computation of Dynamic Current Drain in Presence of Interconnect Capacitive Coupling: a Method

IP.com Disclosure Number: IPCOM000125665D
Publication Date: 2005-Jun-10
Document File: 6 page(s) / 127K

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The IP.com Prior Art Database

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Anuj Singhania: AUTHOR [+2]

Abstract

The effects of capacitive coupling on dynamic current drain in an integrated circuit are investigated and a simplified effective capacitance model is derived. The derived model is then used to devise an algorithm to estimate dynamic power consumption in synthesizable synchronous circuits.

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Computation of Dynamic Current Drain in Presence of Interconnect Capacitive Coupling: a Method

   Anuj Singhania & Arijit Dutta Freescale Semiconductors India Pvt. Ltd.

 Abstract -- The effects of capacitive coupling on dynamic current drain in an integrated cir- cuit are investigated and a simplified effective capacitance model is derived. The derived model is then used to devise an algorithm to esti- mate dynamic power consumption in synthesiz- able synchronous circuits.

I. INTRODUCTION

Current drain has begun to compete with classical design constraints like timing and cost in integrated circuits designed for portable mobile applications such as cellphones and notebooks. Fancier process- ing-intensive applications in real time require high clock speeds and faster devices. This leads to an increase in current drain, thereby reducing battery life. Various power optimization techniques are in vogue in the IC industry today. These have inherent costs and the choice of a combination of optimiza- tion techniques depends on the application. More- over, an accurate estimate of current drain is also a must.

 Current drain in a circuit is the sum of two broad types, viz a) dynamic and b) leakage. Dynamic current drain relates to the portion of the circuit which is active and is caused by transitioning gates. The dynamic current drain can again be classified into a) switching and b) short circuit phenomena. Both these are dependent on the capacitive loading as seen by a switching gate. The capacitive compo- nent of the load is largely a function of the driven interconnect. This is essentially a parasitic capaci- tance and captures all interactions among the dif- ferent metal lines and substrate. In 90 and 65nm technologies the mutual capacitance between neighbouring metal lines (coupling capacitance) often dominates the total parasitic capacitance associated with an interconnect. Therefore, dynamic current drain cannot be estimated accu- rately unless the coupling capacitance is taken into account. Current EDA tools model the coupling

capacitance as ground capacitance. However, we will show that this modelling strategy fails to accu- rately capture the effects of coupling on dynamic current drain. In this paper we propose an algo- rithm to accurately compute dynamic current drain taking into account interconnect coupling.

II. BACKGROUND

 Dynamic power consumption of a gate depends on the following factors:

1.Output capacitive load as seen by the gate
2.Input transition time at the gate input The components of dynamic power are:
1.Short circuit power: Current drain when there exists a direct path between vdd and ground through ON PMOS and NMOS in series
2.Switching power: Current drain due to capaci- tive charging and discharging

1.Capacitance internal to the gate
2.Capacitance external to the gate The short circuit and internal capacitance switch- ing power of a gate is modelled in Synopsys library files in form of lookup tables that depend on inpu...