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Power On Reset Circuit with Zero Steady State Current

IP.com Disclosure Number: IPCOM000125667D
Publication Date: 2005-Jun-10
Document File: 4 page(s) / 2M

Publishing Venue

The IP.com Prior Art Database

Related People

Qadeer Ahmad Khan: AUTHOR [+2]

Abstract

A Power on Reset circuit that does not consume any current in steady state is proposed. The circuit can detect both ramp up and ramp down of supply voltage and the detection threshold is ramp rate independent. The circuit can be used in chips with multiple power supplies and predefined power sequencing.

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Power On Reset Circuit with Zero Steady State Current

Qadeer Ahmad Khan, Divya Tripathi

 

Abstract: A Power on Reset circuit that does not consume any current in steady state is proposed. The circuit can detect both ramp up and ramp down of supply voltage and the detection threshold is ramp rate independent. The circuit can be used in chips with multiple power supplies and predefined power sequencing.

1. INTRODUCTION

A circuit for power supply detection with reduced leakage current is proposed.  This concept can be used for power on reset generation in chips with multiple supplies.  Mostly the chips have separate I/O and core supplies and follow a predefined power up sequence.  I/O supplies are brought up first followed by digital logic supplies.  The proposed technique can be used for generating power on reset signals for the chip.  Also it can be used in circuits, which support hot plug in feature.  In case control signals are at a supply voltage different from the device supply it is required to detect the presence of supply voltage.

2. FUNCTIONAL DESCRIPTION

The proposed Power On Reset (POR) circuit includes a detector that is supplied by a first power supply (OVDD).  The supply to the detector stage is kept lower than the input supply voltage VDD to reduce leakage currents when the supply has ramped up fully.  This is done by applying a reference voltage VREF to a gate of a NMOS transistor connected in series in the supply path.  The source voltage always remains less than the reference voltage.  After the supply voltage has ramped up fully there isn’t any steady state current flowing, as the supply voltage of detector is less than it’s input.  The major advantage of this circuit is negligible current consumption, and ramp rate independent control of ramp up and ramp down detection voltage.  Reduced complexity and ease of design are other major advantages.

Fig.1. Proposed power detection circuit

3. APPLICATIONS

1.        Ramp rate independent power on reset circuit with zero stead...