Browse Prior Art Database

Integration of Charge Pump Capacitor in MRAM Package or Magnetic Shield

IP.com Disclosure Number: IPCOM000125703D
Original Publication Date: 2005-Jul-10
Included in the Prior Art Database: 2005-Jul-10
Document File: 3 page(s) / 61K

Publishing Venue

Siemens

Related People

Juergen Carstens: CONTACT

Abstract

Figure 1 shows a magnetic tunnel junction (MTJ). A stack of two ferromagnetic layers ML separated by a tunnel barrier TL is at the cross-point of two conductors (WL, BL). One of the two magnetic layers is called the free layer. The magnetic orientation of the free layer can be changed by the superposition of the magnetic fields caused by the programming currents IWL and IBL in the conductors WL and BL. However, the magnetic orientation of the fixed magnetic layer cannot be changed by the programming currents IWL and IBL. A bit (0/1) is stored in the MTJ by changing the orientation of the free magnetic layer relative to the fixed magnetic layer. If both magnetic layers have the same orientation, the MTJ has a low resistance RC. The resistance RC is high, if the magnetic layers have opposite magnetic orientations. The memory cell of Fig. 1 can be used together with a select transistor in a 1-Transistor-1MTJ configuration (1T1MTJ cells). A second common array approach is the MRAM cross-point architecture where the MTJs are used without select device. A general problem for MRAM memories is the fact that the memory cells are programmed by PRG (programming) currents in the WLs and BLs which are usually in the mA range. Thus the PRG currents create a significant voltage drop over the WLs and BLs during the PRG operation. This creates problems as for future process technologies the supply voltage is steadily decreasing. However, there is a strong tendency that the voltage over the programmed WLs and BLs is increasing due to an increase of resistance in future technologies. The reason for this is that the widths of WLs and BLs will decrease if technology is scaled to smaller dimensions. Moreover, there is always a tendency for WLs and BLs to become longer in order to increase area efficiency of a memory. For future MRAM chips it will be difficult to supply sufficiently high voltages in order to create the necessary PRG currents.

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Integration of Charge Pump Capacitor in MRAM Package or Magnetic Shield

Idea: Dr. Daniel Braun, FR-Paris; Dr. Dietmar Gogl, US-Essex Junction

Figure 1 shows a magnetic tunnel junction (MTJ). A stack of two ferromagnetic layers ML separated by a tunnel barrier TL is at the cross-point of two conductors (WL, BL). One of the two magnetic layers is called the free layer. The magnetic orientation of the free layer can be changed by the superposition of the magnetic fields caused by the programming currents IWL and IBL in the conductors WL and BL. However, the magnetic orientation of the fixed magnetic layer cannot be changed by the programming currents IWL and IBL. A bit (0/1) is stored in the MTJ by changing the orientation of the free magnetic layer relative to the fixed magnetic layer. If both magnetic layers have the same orientation, the MTJ has a low resistance RC. The resistance RC is high, if the magnetic layers have opposite magnetic orientations. The memory cell of Fig. 1 can be used together with a select transistor in a 1-Transistor- 1MTJ configuration (1T1MTJ cells). A second common array approach is the MRAM cross-point architecture where the MTJs are used without select device.

A general problem for MRAM memories is the fact that the memory cells are programmed by PRG (programming) currents in the WLs and BLs which are usually in the mA range. Thus the PRG currents create a significant voltage drop over the WLs and BLs during the PRG operation. This creates problems as for future process technologies the supply voltage is steadily decreasing. However, there is a strong tendency that the voltage over the programmed WLs and BLs is increasing due to an increase of resistance in future technologies. The reason for this is that the widths of WLs and BLs will decrease if technology is scaled to smaller dimensions. Moreover, there is always a tendency for WLs and BLs to become longer in order to increase area efficiency of a memory. For future MRAM chips it will be difficult to supply sufficiently high voltages in order to create the necessary PRG currents.

A solution to produce the required currents for MRAM PRG operation is the use of charge pumps which generate the required voltages and currents from the supply voltage of the chip. However, for MRAM memories the charge pump approach using on-chip capacitors (e.g. like for Flash memories) is not possible. PRG currents in the mA range would require huge capacitors and therefore large amounts of chip area. An efficient and competitive memory design would not be possible. So the required large capacitances necessary for the charge pumps are not integrated on silicon. The charge pump capacitors are realized as discrete external devices connected to the memory chip.

As the charge pump capacitances cannot be integrated on chip, external devices have to be used. In order to save cost of the MRAM chip, the capacitors have to be implemented as efficiently as possible. A preferable w...