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Reducing Control Signals Storage requirements in Pipelined Designs

IP.com Disclosure Number: IPCOM000125739D
Publication Date: 2005-Jun-15
Document File: 2 page(s) / 52K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method that increases overall storage by reducing the amount of control information stored in the first-in-first-out (FIFO)

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Reducing Control Signals Storage Requirements in Pipelined Designs

Disclosed is a method that increases overall storage by reducing the amount of control information stored in the first-in-first-out (FIFO).

Background

Most current high-performance designs use pipelining techniques to enhance performance. Pipelining is achieved by connecting a number of sequential “pipeline stages”, such that each stage performs the required function in a desired amount of time. Data and control information is passed from one pipeline stage to another and the fully processed data and information is available at the end of the pipeline (see Figure 1).

Most of these pipeline designs operate on large data widths. Moreover, a number of control signals are passed from one pipe stage to another. Depending on the number of clock cycles and pipeline stages required to finish the operation, FIFOs are used to store the intermediate data (see Figure 2). Since the control signals must flow with the corresponding data signals, the control signals are stored in the FIFO. Consequently, each pipe stage needs a number of memory elements to store the data and control information. This increases the amount of storage required, and may result in an increase in the silicon area of an integrated circuit.

General Description

The disclosed method assumes that control signals—like error reporting signals—are in a de-asserted state. Moreover, once these signals are asserted, the pipeline must be flushed and re...