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Highly efficient low temperature emitter

IP.com Disclosure Number: IPCOM000126223D
Original Publication Date: 2005-Aug-10
Included in the Prior Art Database: 2005-Aug-10
Document File: 2 page(s) / 1M

Publishing Venue

Siemens

Related People

Juergen Carstens: CONTACT

Abstract

In power semiconductor devices the current path is running vertically through the semiconductor material. On both sides of the semiconductor material doped regions (p or n) must be generated and activated to guarantee the electrical contacting of emitter and collector region. As shown in figure 1, hitherto existing semiconductor manufacturing processes use first implantation and then thermal annealing to generate these doped regions. These processes usually implicate temperatures up to 800°C for activation and to remove end of range (EOR) defects for achieving high emitter efficiency. If the temperature stays low only Solid Phase Epitaxie (SPE)-regrowth of the amorphous region takes place. The EOR defects though can not be annealed and still remain in the EOR-region below the emitter. EOR defects retard the flow of carrier through the material and force recombination which limits emitter efficiency. In order to put the manufacturing process of the back sided emitter-layer at the end of the whole process and to process thin wafers, it is necessary to use a low temperature anneal like Solid Phase Epitaxie (SPE) but on condition that the emitter-efficiency is high.

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Highly efficient low temperature emitter

Idea: Dr. Thomas Rupp, AT-Villach; Michael Diez, AT-Villach

In power semiconductor devices the current path is running vertically through the semiconductor material. On both sides of the semiconductor material doped regions (p or n) must be generated and activated to guarantee the electrical contacting of emitter and collector region. As shown in figure 1, hitherto existing semiconductor manufacturing processes use first implantation and then thermal annealing to generate these doped regions. These processes usually implicate temperatures up to 800°C for activation and to remove end of range (EOR) defects for achieving high emitter efficiency. If the temperature stays low only Solid Phase Epitaxie (SPE)-regrowth of the amorphous region takes place. The EOR defects though can not be annealed and still remain in the EOR-region below the emitter. EOR defects retard the flow of carrier through the material and force recombination which limits emitter efficiency.

In order to put the manufacturing process of the back sided emitter-layer at the end of the whole process and to process thin wafers, it is necessary to use a low temperature anneal like Solid Phase Epitaxie (SPE) but on condition that the emitter-efficiency is high.

This problem is solved as described below and shown in figure 2. If Pre-Amorphization-Implantation (PAI) or in-situ amorphization on the back side is used applying a mask, only local amorphized regions would be generated. In a...