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Scan Chain Diagnostics Using Internal Latch Observations

IP.com Disclosure Number: IPCOM000126465D
Original Publication Date: 2005-Jul-19
Included in the Prior Art Database: 2005-Jul-19
Document File: 4 page(s) / 95K

Publishing Venue

IBM

Abstract

The complex of very large-scale integrated circuits contain very large number of logic circuits that require extensive testing. In order to mitigate the complexity of the testing required, scan based designs have been implemented. Generally, the drawback of the scan based design test methodology is encountered when the scan chain is not functioning properly and access to the internal logic of the device is greatly reduced, thereby severely complicating the diagnostic process and inhibiting rapid determination of the problem's root cause. This type of problems are usually encountered early in the technology's life cycle and their diagnosability is critical in improving the process so it quickly achieves manufacturing yield levels. This invention proposes a solution to the problem of testing and diagnosing broken or stuck-at scan chains and rapidly diagnosis to a physical location for Physical Failure Analysis (PFA) to understand and correct the process anomalies

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Scan Chain Diagnostics Using Internal Latch Observations

This invention provides another tool used as part of an arsenal to diagnose broken scan chain(s). This invention proposes a solution to aid in the diagnostics of broken scan chains. Broken scan chain diagnostics are usually performed early in the technology's life cycle and is imperative that rapid diagnosis to a physical location is needed to understand and correct the manufacturing process.

     Before describing the invention to the problem of diagnosing broken scan chains, a short overview of the level sensitive scan design (LSSD) scan based design and test methodology is illustrated in Figures 1 and 2. In a scan based design, all the latches in a shift register (SR) are accessible via serial access. In LSSD, most of the latches or registers are concatenated in one or more scan chains and are externally accessible via one or more serial inputs and outputs as illustrated in Figures 1 and 2. LSSD latches are designed in a L1/L2 configuration in which the L1 or master latch has two data ports and may be updated either by a scan clock (A clock) or a functional system clock (C1 clock). The L2 or slave latch has a scan clock input (B clock) and the system clock (C2 clock) and these clocks are out of phase with both the L1 clocks. Scan operations are performed using separate A and B clocks and chip testing uses C1 and C2 clocks as illustrated in Figure 2.

     Most common failure mechanism early in the technology is broken scan chains. A solution(s) which is rapid, efficient, and speeds up diagnostics eventually will improve yield insuring successful production of the design.

     The LSSD Flush test consists of both the A clock and the B clock being turned on (and stay on) at the same time.The value on the scan-in line will propagate through all SRLs to the scan-out line. The main purpose of the Flush test is to detect as many defects in the SR as quickly as possible.

     The LSSD Scan test consists of a string of alternating logic "0"s and logic "1"s ( 00 11 00 11 .. .. ) that are stepped through the SR by pulsing the A and B clocks and changing values on the scan-in line. The intent of this test is to detect defects in the SR that were not picked up during the Flush test. An example of this kind of fault would be one that causes a clock line to stay on.

     The FLUSH and SCAN test will fail when there are broken scan chain(s) on the device. In this case, there is no operating region. Different approaches that allow the flush and scan tests to pass include slower tester rates, wider scan A and B clock pulse widths and/or separations. If an operating region exists, AC scan diagnostics methods can then be utilized. The problem is to identify where the DC break is located within the scan chain. Since all other tests utilize the scan chain to perform a multitude of subsequent chip tests, diagnosing DC flush and scan fails are extremely limited. Fault simulation which is one tool used for diagnosing det...