Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Method Of Using I2C Logical Adapters In Blade Center

IP.com Disclosure Number: IPCOM000126474D
Original Publication Date: 2005-Jul-20
Included in the Prior Art Database: 2005-Jul-20
Document File: 4 page(s) / 93K

Publishing Venue

IBM

Abstract

Disclosed is a method of using logical I2C adapters present in Blade Center for System Management Application. The device driver abstracts logical I2C adapters as physical adapters enabling applications to access I2C devices seemlessly whether the devices are present on physical adapter or logical adapters. In a blade center system, the I2C subsystem is very complex having a large number of logical adapters connected to a few physical adapters of the management module controller. Usually the management module may have 1-4 physical adapters, the number of logical adapters can range 10-40 or more. The I2C devices are present on both physical and logical adapters. This solution makes the applications easily access the I2C devices and more portable. In addition, OEM vendors can write applications easily for their module(switch, bridge etc) in blade center.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 57% of the total text.

Page 1 of 4

Method Of Using I2C Logical Adapters In Blade Center

     The I2C adapters present on the CPU of management module controller represent the hardware controllers and they are called primary(physical) adapters in this disclosure. The logical adapters are derived from primary adapters by means of I2C bus expander. Each of the expander is an I2C device that acts as demultiplexor of the input I2C bus. The combination of primary adapters and logical adapters constitutes a tree of I2C adapters, that is used in our blade center design.

One representation is shown below:

LB16

I2C Dev3

I2C_Dev2

LB1

Logical Adapters

PB0

MUX_0 (1:4) PCA9545

0xE6

I2C - 0

PPC CPU

I2C - 1

I2C Dev5

LB5

LB6

I2C_Dev 1

LB4

MUX_1 (1:4) PCA9546

0xE0

LB9

LB7

I2C Dev6

PB1

LB8

MUX_2 (1:8) PCA9548

0xE2

LB10

I2C Dev4

LB17

MUX_3 (1:8) PCA9548

0xE2

LB18

Primary Adapters

LB24

     As shown above, the CPU has two primary adapters in PB0/PB1. However, a number of logical adapters have been created using the I2C bus expanders also called multiplexors. The first multiplexor creates logical adapters LB1-LB4 off the PB0. The second multiplexor present on LB4 creates further logical adapters in LB5-LB8, the third multiplexor generates buses LB9-LB16 and the fourth one creates LB17-LB24. It is possible to have more logical buses off any of the above logical buses making the design more complex. As shown above, all logical adapters are derived from PB0, so PB0 is the root adapter for all the logical adapters. In some system design, it is possible to have some logical adapters generated by each of the primary adapters.

     In general, an I2C device is accessed off a primary adapter. The pseudo code for accessing a device present on PB0 is shown in Case1:

Case1:

fd = open("/dev/i2c-0", O_RDWR); //opens the primary adapter PB0 .

ioctl(fd, I2C_SLAVE_ADDR, 0xAA); //it selects device address AA on PB0

read(fd, buf, num); //it reads num bytes from the device

write(fd, buf, num); //it writes num bytes to the device.

close(fd); //it closes the device.

     There is no such method for accessing device on the logical adapter. In some solutions, the application passes the logical adapter number to a library. The library

1

Page 2 of 4

uses that information for set up the multiplexors one at a time.The application then initiates the read/write transaction.

     In this proposed solution, each logical adapter can be abstracted as primary adapter. For each of the logical adapters, there are associated properties stored in a structure that define the relationship to its root adapter. Then the access can be done as it is done for any primary adapter. The associated bus properties contain information about the chain of multiplexor present in its path from the root adapter. The associated properties are stored once in the beginning for every new system, as they may be unique from system to system. The pseudo code for accessing I2C_Dev6 is shown as below:

Case2:

fd = open("/dev/i2c-6", O_RDWR); //opens the logical adapter LB6

io...