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Adaptive MTCMOS for Dynamic Leakage and Frequency Control Using Variable Footer Strength

IP.com Disclosure Number: IPCOM000126498D
Original Publication Date: 2005-Jul-21
Included in the Prior Art Database: 2005-Jul-21
Document File: 5 page(s) / 138K

Publishing Venue



Deviations in leakage and delay due to process variation have increased greatly with technology scaling. Presented are two adaptive MTCMOS schemes to address the growing leakage and delay spreads found in modern high-performance designs. Variable-Gate Voltage MTCMOS adjusts the applied gate voltage on footer devices while Variable-Width MTCMOS adaptively turns on or off footers in a circuit block. Both techniques compensate for the spread in leakage and delay. Results show a 21%-61% decrease in runtime leakage with a worst-case delay penalty of 9%.

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Adaptive MTCMOS for Dynamic Leakage and Frequency Control Using Variable Footer Strength

  Simulations of process variation in an industrial sub-100nm SOI technology, seen in Fig. 1, show the spread in frequency and runtime leakage of a 32-bit adder block due to variations in the channel length and

0.90 0.95 1.00 1.05 1.10









~20% Spread

Normalized Leakage

Normalized Delay

Figure 1: Frequency and leakage spread of a circuit block.

threshold voltage (DIBL). The frequency of the circuit block has a 20% spread over the process corners while the runtime leakage has a spread of 6X. Such large spreads in frequency and leakage make it difficult to effectively meet the timing and power constraints of a circuit block. MTCMOS is a popular standby leakage reduction technique for power-constrained applications; we study it in the context of two new areas in this paper: 1) Proposed are two variable strength MTCMOS schemes that adaptively compensate for process variation, alleviating the need for a worst-case design strategy, and 2) When examined, the effects of virtual ground bounce to reduce runtime leakage in MTCMOS implementations.

  The Variable-Gate Voltage MTCMOS (VGV-MTCMOS) design applies a variable gate-to-source voltage on the footer device, as seen in Fig. 2. If the process is tilted towards the fast corner, then the applied gate voltage on the footer device is lowered. Consequently, the amount of current that the device can sink is reduced, slowing down the circuit block to its nominal delay point. Moreover, since the footer device is now only weakly on, its resistance increases which then increases the average ground bounce on the virtual ground line. This rise in the average ground bounce reduces the leakage power consumption in the steady-state devices in the circuit block as described in Section II.

~6X Spread


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When the process is tilted towards the slow corner, the footer device is fully turned on and the circuit block behaves as it would in the nominal base slower corner case. Our VGV-MTCMOS implementation allows for selecting up to five discrete gate voltages, depending on where the process lies between fast and slow corners. These gate voltages represent five discrete footer pull-down strengths.

Critical Path

Gate Voltage Selector

Counter Out

Figure 2: Block diagram of VGV-MTCMOS.

  The Variable-Width MTCMOS (VW-MTCMOS) design incorporates several footer devices that can be turned on or off individually, as seen in Fig. 3. As the process tilts from one corner to the other, a different number of footers can be turned on or off to provide a varying level of current sinking capability. In standby mode, all footers are turned off as in the normal case for power gating.

  For a die at the fast corner, the number of footers on during the active mode is decreased, reducing the total pull down width. This reduces the current sinking capability of the footer and consequently increases the delay of t...