Browse Prior Art Database

Self Read of Memory Devices with Variable Compressed Read Data

IP.com Disclosure Number: IPCOM000126653D
Original Publication Date: 2005-Aug-25
Included in the Prior Art Database: 2005-Aug-25
Document File: 1 page(s) / 43K

Publishing Venue

Siemens

Related People

Juergen Carstens: CONTACT

Abstract

With increasing memory capacity, the data transfer time of the complete memory data increases due to the fact that the interface speed is not increasing in the same scale. This means for production testing that the test costs are increasing. The idea is to reduce the number of data which have to be transferred to the test equipment. The device generates the expected data (different pattern) on chip, compares it after array sensing with the read data and latches the pass/fail information. The read operation is automatically performed by the device (“Self Read”) over a certain part of the array. A schematic of this mechanism is shown in Fig. 1. There are different requirements for pass/fail latching (in terms of granularity) depending on the test flow, e.g.: • certain granularity needed to fit the memory repair resolution • pass/fail information needed of complete device, e.g. functional testing after array repair • pass/fail information of a certain array region needed for some algorithms e.g. reference cell program of flash devices or as workaround due to defect area (technology issue)

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Self Read of Memory Devices with Variable Compressed Read Data

Idea: Volker Zipprich-Rasch, DE-Dresden

With increasing memory capacity, the data transfer time of the complete memory data increases due to the fact that the interface speed is not increasing in the same scale. This means for production testing that the test costs are increasing.

The idea is to reduce the number of data which have to be transferred to the test equipment. The device generates the expected data (different pattern) on chip, compares it after array sensing with the read data and latches the pass/fail information. The read operation is automatically performed by the device ("Self Read") over a certain part of the array. A schematic of this mechanism is shown in Fig. 1.

There are different requirements for pass/fail latching (in terms of granularity) depending on the test flow, e.g.:

* certain granularity needed to fit the memory repair resolution

* pass/fail information needed of complete device, e.g. functional testing after array repair

* pass/fail information of a certain array region needed for some algorithms e.g. reference cell program of flash devices or as workaround due to defect area (technology issue)

The term (repair) granularity denotes the overlapping area of redundant bit- and wordlines. Memory devices have such redundancy elements to be able to replace a certain number of defect bitlines and wordlines.

In the proposed solution, the pass/fail information is latched after...