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Architectural and Microarchitectural Attribute Extraction and Analysis for Simulation-based Functional Verification of Integrated Circuit Designs

IP.com Disclosure Number: IPCOM000126677D
Original Publication Date: 2005-Jul-28
Included in the Prior Art Database: 2005-Jul-28
Document File: 3 page(s) / 407K

Publishing Venue

IBM

Abstract

Disclosed is a software system architecture and method for extracting a test program's architectural constructs and properties pertinent to functional verification of integrated circuit designs such as Processors, ASICs, SoCs, and Silicon IPs. The disclosed system utilizes standard Instruction set simulators or architecture simulators and assembly code debuggers to convert a test program to a standards test attribute format. This enables development of standard tools and methods for functional verification and coverage analysis of integrated circuits. One such verification and analysis platform that utilizes the disclosed test analyzers and attribute generators is described in [1].

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Architectural and Microarchitectural Attribute Extraction and Analysis for Simulation-based Functional Verification of Integrated Circuit Designs

Majority of processor, ASIC, SoC, and Silicon IP designs are verified by using one or more simulation-based techniques, which utilize some form of test program either generated manually by engineers or automatically by test generators as shown in Figure 1.

     Functional verification and coverage analysis tools are usually developed for a specific test format and require substantial modification to support a different test format. We disclose a system and method which utilize Instruction set simulators and assembly code debuggers to convert a test program to a standard test attribute format by; 1) Extracting explicit design architecture constructs and verification attributes, 2) Computing implicit test attributes such as data types, address ranges, true and false sharing, data and architectural resource dependencies, etc. and 3) Compiling the above in a standard format (such as IBM's DVA - Design & Verification Attributes ) ready for analysis as shown in Figure 1. The system and methods disclosed here are a component of the verification and analysis platform disclosed in [1].

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Figure 1: A Verification and Analysis Environment Based on the Disclosed Test Signature Generators

     Test Program Analysis and Test Attribute (Signature) Generation: A test signature analyzer/generator is a program that takes a test or a simulation dump including environment attributes and the stimulus as input. It then extracts architectural design constructs and properties from the test according to the target format and configuration. It also generates or calculates other design and verification attributes from the analysis of test structure, content, and attributes. Microarchitectural attributes are extracted from simulation (traces) and the result is compiled in the target test signature format (such as IBM's DVA format utilized in the verification and analysis platform described in [1]). Three such test analyzer/DVA generators are shown in Fig. 1 (TST2DVA, MAN2DVA, VCD2DVA) and further described in the following sections.

     1) TST2DVA is an example of a test analyzer/signature generator for tests written in the IBM TST format [2]. The majority of IBM test generators and simulators support TST format [3].

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