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GDSII based Hierarchical Power network analysis for System on Chip designs

IP.com Disclosure Number: IPCOM000126809D
Publication Date: 2005-Aug-02

Publishing Venue

The IP.com Prior Art Database

Related People

Anuj Singhania: AUTHOR [+4]

Abstract

With increasing size of the SoC designs, it is imperative to use Hierarchical Analysis for power grid verification. Many EDA tools offer hierarchal power grid analysis flow. All of these tools involve resistance extraction of powergrid network. Accuracy of hierarchical analysis is directly dependent upon the interface connections from toplevel grid to block grid. Present day tools extract this information from the design specifications rather than using GDSII which has complete information of chip layout. In this document, we propose a method to accurately identify the interface nodes in the design. This step is integral part of our proposed Hierarchal Analysis flow which also involves a unique technique to reduce the size of data to be handled by extraction tool.

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GDSII based Hierarchical Power network analysis for System on Chip designs

Anuj Singhania, N Kannan, Rohit Gupta, Ajit Kumar Freescale Semiconductor

Abstract

With increasing size of the SoC designs, it is imperative to use Hierarchical Analysis for power grid verification. Many EDA tools offer hierarchal power grid analysis flow. All of these tools involve resistance extraction of powergrid network. Accuracy of hierarchical analysis is directly dependent upon the interface connections from toplevel grid to block grid. Present day tools extract this information from the design specifications rather than using GDSII which has complete information of chip layout. In this document, we propose a method to accurately identify the interface nodes in the design. This step is integral part of our proposed Hierarchal Analysis flow which also involves a unique technique to reduce the size of data to be handled by extraction tool.

1 INTRODUCTION

In present generation SoCs, the shrinking device sizes has resulted in a big increase in the gate count. This has necessitated the design of dense power networks. Since Voltage drop and Electromigrtaion are important considerations in the SoC design, the analysis of the power network is essential for ensuring successful functioning of the design. The earlier approach was to carry out flat analysis. But this approach is being discarded due to the inability of existing EDA (electronic design automation) tools to handle the large datasize involved. The approach has been to move to hierarchical analysis of the power network.

In SoC designs the power grid planning begins at the Floor planning stage itself but usually the power grid gets final shape only in the physical layout (GDSII). Additional connections between top level power grid and a blocks power grid can also be made in the layout. These connections may not be present in the original specifications.The connections from toplevel powergrid to block powergrid is henceforth referred as interface nodes in this document. Thus a flow is needed to analyze the power grid information obtained from the GDSII only, without any presumptions. The use of GDSII for obtaining the power network will result in increase in the datasize to be handled. This consequently results in large run times and heavy hardware requirements. These are issues which need to be addressed by any GDSII based power network analysis flow.

The problem is formally defined in section 2. Section 3 we describe the flow to obtain interface connections from GDSII. Section4 details the proposed flow for accurate hierarchical power grid analysis. Section 5 contains the results for the analysis which we had carried out to compare the IR drop analysis results obtained using the proposed flow with the analysis done using the existing flow. Comparison has also been done with flat power network analysis to show the accuracy of the proposed flow.

1 Freescale Semiconductor Confidential Proprietary

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