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Method and System to Accurately Incorporate Effects of Gate Input Capacitance Variation in Static Timing Analysis

IP.com Disclosure Number: IPCOM000126810D
Publication Date: 2005-Aug-02
Document File: 8 page(s) / 124K

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The IP.com Prior Art Database

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Arijit Dutta: AUTHOR [+3]

Abstract

The effect of input slew and output capacitive loading on input gate capacitance of a digital circuit has been explained. The effect of varying input gate capacitance on propagation delay is then analyzed and a cost effective and accurate algorithm is derived to incorporate such variation in Static Timing Analysis.

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Method and System to Accurately Incorporate Effects of Gate Input Capacitance Variation in Static Timing Analysis

Arijit Dutta, Bhuwan Agrawal & Nand Kishore Jha Freescale Semiconductors India Pvt. Ltd.

 Abstract -- The effect of input slew and output capacitive loading on input gate capacitance of a digital circuit has been explained. The effect of varying input gate capacitance on propagation delay is then analyzed and a cost effective and accurate algorithm is derived to incorporate such variation in Static Timing Analysis.

I. INTRODUCTION

Competitive markets and steadily increasing cus- tomer demands are propelling portable wireless applications like cellphones to evolve at a rapid pace. Gone are the days when we needed cell- phones to make just voice calls and send text mes- sages. Current generation phones not only have funky colour displays and camera, but are also packed with multimedia applications and pda-like features. Needless to mention that all this would not have been possible without comparable evolu- tion in associated chipsets. Computation intensive applications need faster processing rates. Increas- ing feature-sets lead to large volumes and data stor- age and management. All this needs to be done without increasing the size of applications (espe- cially cellphones). At the same time, consumers still demand comparable or better talk and standby times. Oh, and the biggest constraint: reasonable cost!

From a technical standpoint, the above require- ments translate to higher circuit speed, sophisti- cated power management techniques, multiple levels of cache and memory and shrinking device sizes. Timing closure in sub-100nm technologies with its associated UDSM effects like signal integ- rity and on-chip-variation of process, temperature and voltage is becoming more and more difficult. The ASIC and microprocessor design industry is in the process of exploring techniques like statistical timing analysis to address the timing closure prob- lem and link it to silicon yield. However, although

we are at the threshold of CMOS65, EDA vendors are yet to come up with a viable commercial solu- tion for SSTA. This leaves organizations to solve the UDSM timing issues with clever workarounds in conjunction with existing toolsets. Sub-100nm technologies are exhibiting a hitherto unknown property - the input gate capacitance shows signifi- cant variation as a function of gate input slew rate and gate output loading.

Here we will explain the above problem from a his- torical perspective, provide data to prove its criti- cality and attempt to come up with a viable solution that is cost effective and reasonably accu- rate.

II. BACKGROUND

 Synthesizable, gate-based design methodologies use characterized libraries to model gate behaviour from various aspects. One very common abstrac- tion is the timing view that models gate timing behaviour in a context-independent fashion. The most widely used format for modelling gate timing behaviour...