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SHARED PERSISTENT MEMORY LOGIN DUAL PROCESSING ARCHITECTURE

IP.com Disclosure Number: IPCOM000126840D
Publication Date: 2005-Aug-15
Document File: 1 page(s) / 22K

Publishing Venue

The IP.com Prior Art Database

Abstract

Shared persistent memory to log processor states/boot-up failure cause in a dual-processor architecture for recovering from or debugging of issues when inter-processor communication does not or cannot get established In a dual-processor architecture, there is no effective and easy mechanism to debug issues when inter-processor communication does not get established between the two processors for hardware/software reasons. There are currently two debugging mechanisms in existence: one reviews the logs that are maintained in some persistent memory by individual processor, and the other debugs the hardware if logs are not accessible. Neither of the above methods provides an easy and effective way to debug issues that prevent inter-processor communication links from getting established in a dual-processor architecture. The following mechanism is recommended to alleviate problems mentioned above: • One with a persistent memory where both of the processor will have access to it. • The persistent memory will be used by both processors to log important processor states and critical failure causes. These states will include primary states that each processor goes through prior to the inter-processing link coming up. • Persistent memory size can be small, as only failure codes and state codes need to be logged. Mechanism must exist for concurrency control, since both of the processors are running asynchronously. • If one processor fails to boot up, resets or shuts down while booting, the other processor can access the log information by entering into a particular software mode to determine the cause of the failure. • The persistent memory can be used for post-mortem in case the device has been returned or when both of the processors fail to function. • As the persistent memory will log the sequence of events between the two processors, it will be simple to identify when the failure occurred. The failure code, along with the “when failure information” will provide details of the cause. It should be noted that this idea can be extended to multi-processor architectures.

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SHARED PERSISTENT MEMORY LOGIN DUAL PROCESSING ARCHITECTURE

Shared persistent memory to log processor states/boot-up failure cause in a dual-processor architecture for recovering from or debugging of issues when inter-processor communication does not or cannot get established

Disclosed Anonymously

In a dual-processor architecture, there is no effective and easy mechanism to debug issues when inter-processor communication does not get established between the two processors for hardware/software reasons.  There are currently two debugging mechanisms in existence: one reviews the logs that are maintained in some persistent memory by individual processor, and the other debugs the hardware if logs are not accessible. 

Neither of the above methods provides an easy and effective way to debug issues that prevent inter-processor communication links from getting established in a dual-processor architecture. 

The following mechanism is recommended to alleviate problems mentioned above: 

  • One with a persistent memory where both of the processor will have access to it.
  • The persistent memory will be used by both processors to log important processor states and critical failure causes.  These states will include primary states that each processor goes through prior to the inter-processing link coming up.
  • Persistent memory size can be small, as only failure codes and state codes need to be logged.  Mechanism must exist for concurrency control, since both of the processors are running a...