Designing a PCI card on the PCI Compatibility bus slot to do POST/BIOS flash ROM emulation and programming
Original Publication Date: 2005-Aug-16
Included in the Prior Art Database: 2005-Aug-16
The POST/BIOS code for most computer systems resides on a Flash ROM chip and is the first set of code to bringup a computer. During the code development, the software engineers have to remove the Flash ROM from the mother board and program the code using a programming device like DATA IO or BP programmer. After diskette drive has been successfully configured, the Flash ROM code can be updated through a diskette with POST/BIOS image. In either case, it may take more than 10 minutes for each code update. There are some Romulator available which downloads code from the computer containing the code image to a SRAM device. The computer under code development will fetch instructions from the SRAM through a cable which is connected to a on-board connector or the Flash ROM socket directly using a custom made head attached to the connector. The Flash ROM update becomes unnecessary, at least during code development, because the code is in SRAM. This will only takes less than 10 second for 1MB code to turn around and help to increase the code development efficiency. However, the connector for SRAM access will cost more than $1.00 and occupy a space on the motherboard or it requires a socket and an expensive and not easy installed cable head to directly plug the cable into the socket. To save cost, the production board does not provide either Romulator connector nor Flash ROM socket. This invention is to remove any Romulator design on board by using a Romulator card plugged into the PCI compatibility bus slot. This romulator card not only can emulate the POST/BIOS code effectively and efficiently during the code development, but also can be used for manufactuing for Flash ROM programming and code debugging/repairing for the production computer. In our x-series servers, typically there is a PCI slot in the Compatibility bus for the Service processor card. The POST/BIOS flash ROM are fetched through the South Bridge chip which also attached to the Compatibility bus. The south bridge chip used in x-series are OSB4, CSB6 from ServerWorks or from Via 686B chip. All these chips using the 'subtractive decoding' DEVSEL to claim the transaction for the Memory read command which is the command used in the instruction fetch. If we design a PCI card which claim the Memory read operation to the Flash ROM space using any decoding speed, i.e. FAST, MED or SLOW, the PCI card will take over the South Bridge instruction fetch operation and allow any features designed in the PCI Romulator card to be used in the code development and the Flash ROM programming during development and manufacturing and even after the product is shipped.
Designing a PCI card on the PCI Compatibility bus slot to do POST /BIOS flash ROM emulation and programming
The following Fig. 1 shows the Compatibility bus devices. The PCI Romulator card shown in Fig. 2 will be plugged into the compatibility PCI slot. PCI card contains a FPGA chip which will claim the Memory read operations to the Flash ROM space using FAST DEVSEL speed. The South Bridge chip will not respond to the same Memory read operation because it is a Memory 'subtractive decoding' device but will still respond to other PCI commands like IO read/write. The PCI card, after claiming the Memory operation will generate SRAM bus operation to access either Flash ROM on the card or the SRAM data in the Romulator and send data to the North Bridge chip. The SRAM data are typically used for POST/BIOS emulation during the code development. If Service Processor has to be involved in the code development, the Service Processor can be plugged into the connector on top of the Romulator card. FPGA is able to resolve the IDSEL target for the Romulator card or the Service Processor card and let the two cards run independently.
The Flash memory chip on the card can be used a temporay BIOS/POST code when Romulator is not plugged into the card. Or it may be used as a mother board Flash ROM programming tool. In this case, the Flash memory will contain the programming code with the POST/BIOS image and allow the processor to load the programming code and POST/BIOS image to the main memory and execute the programming code using the POST/BIOS...