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Method to do automatic code recovery for the POST/BIOS using the LPC flash memory

IP.com Disclosure Number: IPCOM000126966D
Original Publication Date: 2005-Aug-16
Included in the Prior Art Database: 2005-Aug-16
Document File: 2 page(s) / 132K

Publishing Venue

IBM

Abstract

LPC flash memory for BIOS code is replacing conventional parallel SRAM type bus flash memory in many computer system. In parallel flash memory system, the BIOS recovery relies on toggling flash memory address bit A20 using a GPIO signal to select the priamry or secondary 1MB BIOS bank. Typically, the primary bank and secondary bank contains identical 1MB of BIOS code. Capability of selecting either bank allows system to select a good BIOS code in one bank while the other bank becomes not readable. This method of toggling A20 using a GPIO signal does not work for the LPC flash memory because the LPC bus is essentially a serialized ISA bus. The address bit A20 of the LPC flash memory is serialized with other address, data and control/status bits and can not be toggled using a GPIO signal like the conventional parallel SRAM bus type flash memory.

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Method to do automatic code recovery for the POST /BIOS using the LPC flash memory

     The following diagram shows a typical 4 MB LPC flash memory design in a computer system. U1 is the LPC host which initiates the LPC bus operation to access the flash memory. U3 and U4 are two 2 MB LPC flash memory modules (the largest LPC memory on the market by far). U3 contains the two versions of POST/BIOS code images with size of 1MB each. The main purpose of two versions of BIOS code is to be able to bringup the system using the backup version (typically, the BIOS code in the secondary bank) when the primary version of BIOS becomes unreadible. U4 is for the diagnostic code and there is no need of backup because the code can be updated after BIOS boots up the system. After the system is powered on, it always starts to fetch instructions at the address locations FFFFFFF0 which resides in the primary bank of the BIOS flash memory on the LPC bus. When the LPC flash memory de-serializes the address bits, the ID pins of the flash memory are used to determine the space of the 2MB (e.g. A21, A23-A25 are compared with ID pin signals) of the flash memory. Address bit A20 will determine the primary 1MB (A20=1) and the secondary 1MB (A20=0) in the 2MB flash memory. U3 will be selected when ID(0-3) = 1111 and the LPC host drives the address of "1111_1111_111a_xxxx_xxxx_xxxx_xxxx_xxxx"B during the LPC bus 8 byte address cycles. When bit 'a' (which is bit A20) = 1, the primary bank is selected. When bit 'a' = 0, the secondary bank is selected. Since the system always fetches from address FFFFFFF0H, normally the primary bank BIOS code is selected. When there is a need to fetch instructions from the secondary bank, A20 bit of the LPC operation to the BIOS flash memory must be set to '0' eventhough LPC host still drives A20 to '1'. The following diagram shows the invention of the LPC flash memory automatically selecting the correct 1MB BIOS code by changing the state of A20 during the LPC operation.

     Jumper J1 is the conventional BIOS RECOVERY JUMPER J1. When J1 is jumped to 'high' or a system-accessible bit in a CPL...